1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/ppc/xics.h" 6 7 struct VIOsPAPRBus; 8 struct sPAPRPHBState; 9 struct sPAPRNVRAM; 10 11 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 12 13 typedef struct sPAPREnvironment { 14 struct VIOsPAPRBus *vio_bus; 15 QLIST_HEAD(, sPAPRPHBState) phbs; 16 struct sPAPRNVRAM *nvram; 17 XICSState *icp; 18 19 hwaddr ram_limit; 20 void *htab; 21 uint32_t htab_shift; 22 hwaddr rma_size; 23 int vrma_adjust; 24 hwaddr fdt_addr, rtas_addr; 25 ssize_t rtas_size; 26 void *rtas_blob; 27 void *fdt_skel; 28 target_ulong entry_point; 29 uint64_t rtc_offset; 30 struct PPCTimebase tb; 31 bool has_graphics; 32 33 uint32_t epow_irq; 34 Notifier epow_notifier; 35 36 /* Migration state */ 37 int htab_save_index; 38 bool htab_first_pass; 39 int htab_fd; 40 bool htab_fd_stale; 41 } sPAPREnvironment; 42 43 #define H_SUCCESS 0 44 #define H_BUSY 1 /* Hardware busy -- retry later */ 45 #define H_CLOSED 2 /* Resource closed */ 46 #define H_NOT_AVAILABLE 3 47 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 48 #define H_PARTIAL 5 49 #define H_IN_PROGRESS 14 /* Kind of like busy */ 50 #define H_PAGE_REGISTERED 15 51 #define H_PARTIAL_STORE 16 52 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 53 #define H_CONTINUE 18 /* Returned from H_Join on success */ 54 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 55 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 56 is a good time to retry */ 57 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 58 is a good time to retry */ 59 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 60 is a good time to retry */ 61 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 62 is a good time to retry */ 63 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 64 is a good time to retry */ 65 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 66 is a good time to retry */ 67 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 68 #define H_HARDWARE -1 /* Hardware error */ 69 #define H_FUNCTION -2 /* Function not supported */ 70 #define H_PRIVILEGE -3 /* Caller not privileged */ 71 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 72 #define H_BAD_MODE -5 /* Illegal msr value */ 73 #define H_PTEG_FULL -6 /* PTEG is full */ 74 #define H_NOT_FOUND -7 /* PTE was not found" */ 75 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 76 #define H_NO_MEM -9 77 #define H_AUTHORITY -10 78 #define H_PERMISSION -11 79 #define H_DROPPED -12 80 #define H_SOURCE_PARM -13 81 #define H_DEST_PARM -14 82 #define H_REMOTE_PARM -15 83 #define H_RESOURCE -16 84 #define H_ADAPTER_PARM -17 85 #define H_RH_PARM -18 86 #define H_RCQ_PARM -19 87 #define H_SCQ_PARM -20 88 #define H_EQ_PARM -21 89 #define H_RT_PARM -22 90 #define H_ST_PARM -23 91 #define H_SIGT_PARM -24 92 #define H_TOKEN_PARM -25 93 #define H_MLENGTH_PARM -27 94 #define H_MEM_PARM -28 95 #define H_MEM_ACCESS_PARM -29 96 #define H_ATTR_PARM -30 97 #define H_PORT_PARM -31 98 #define H_MCG_PARM -32 99 #define H_VL_PARM -33 100 #define H_TSIZE_PARM -34 101 #define H_TRACE_PARM -35 102 103 #define H_MASK_PARM -37 104 #define H_MCG_FULL -38 105 #define H_ALIAS_EXIST -39 106 #define H_P_COUNTER -40 107 #define H_TABLE_FULL -41 108 #define H_ALT_TABLE -42 109 #define H_MR_CONDITION -43 110 #define H_NOT_ENOUGH_RESOURCES -44 111 #define H_R_STATE -45 112 #define H_RESCINDEND -46 113 #define H_P2 -55 114 #define H_P3 -56 115 #define H_P4 -57 116 #define H_P5 -58 117 #define H_P6 -59 118 #define H_P7 -60 119 #define H_P8 -61 120 #define H_P9 -62 121 #define H_UNSUPPORTED_FLAG -256 122 #define H_MULTI_THREADS_ACTIVE -9005 123 124 125 /* Long Busy is a condition that can be returned by the firmware 126 * when a call cannot be completed now, but the identical call 127 * should be retried later. This prevents calls blocking in the 128 * firmware for long periods of time. Annoyingly the firmware can return 129 * a range of return codes, hinting at how long we should wait before 130 * retrying. If you don't care for the hint, the macro below is a good 131 * way to check for the long_busy return codes 132 */ 133 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 134 && (x <= H_LONG_BUSY_END_RANGE)) 135 136 /* Flags */ 137 #define H_LARGE_PAGE (1ULL<<(63-16)) 138 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 139 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 140 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 141 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 142 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 143 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 144 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 145 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 146 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 147 #define H_ANDCOND (1ULL<<(63-33)) 148 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 149 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 150 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 151 #define H_COPY_PAGE (1ULL<<(63-49)) 152 #define H_N (1ULL<<(63-61)) 153 #define H_PP1 (1ULL<<(63-62)) 154 #define H_PP2 (1ULL<<(63-63)) 155 156 /* Values for 2nd argument to H_SET_MODE */ 157 #define H_SET_MODE_RESOURCE_SET_CIABR 1 158 #define H_SET_MODE_RESOURCE_SET_DAWR 2 159 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 160 #define H_SET_MODE_RESOURCE_LE 4 161 162 /* Flags for H_SET_MODE_RESOURCE_LE */ 163 #define H_SET_MODE_ENDIAN_BIG 0 164 #define H_SET_MODE_ENDIAN_LITTLE 1 165 166 /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 167 #define H_SET_MODE_ADDR_TRANS_NONE 0 168 #define H_SET_MODE_ADDR_TRANS_0001_8000 2 169 #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 170 171 /* VASI States */ 172 #define H_VASI_INVALID 0 173 #define H_VASI_ENABLED 1 174 #define H_VASI_ABORTED 2 175 #define H_VASI_SUSPENDING 3 176 #define H_VASI_SUSPENDED 4 177 #define H_VASI_RESUMED 5 178 #define H_VASI_COMPLETED 6 179 180 /* DABRX flags */ 181 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 182 #define H_DABRX_KERNEL (1ULL<<(63-62)) 183 #define H_DABRX_USER (1ULL<<(63-63)) 184 185 /* Each control block has to be on a 4K boundary */ 186 #define H_CB_ALIGNMENT 4096 187 188 /* pSeries hypervisor opcodes */ 189 #define H_REMOVE 0x04 190 #define H_ENTER 0x08 191 #define H_READ 0x0c 192 #define H_CLEAR_MOD 0x10 193 #define H_CLEAR_REF 0x14 194 #define H_PROTECT 0x18 195 #define H_GET_TCE 0x1c 196 #define H_PUT_TCE 0x20 197 #define H_SET_SPRG0 0x24 198 #define H_SET_DABR 0x28 199 #define H_PAGE_INIT 0x2c 200 #define H_SET_ASR 0x30 201 #define H_ASR_ON 0x34 202 #define H_ASR_OFF 0x38 203 #define H_LOGICAL_CI_LOAD 0x3c 204 #define H_LOGICAL_CI_STORE 0x40 205 #define H_LOGICAL_CACHE_LOAD 0x44 206 #define H_LOGICAL_CACHE_STORE 0x48 207 #define H_LOGICAL_ICBI 0x4c 208 #define H_LOGICAL_DCBF 0x50 209 #define H_GET_TERM_CHAR 0x54 210 #define H_PUT_TERM_CHAR 0x58 211 #define H_REAL_TO_LOGICAL 0x5c 212 #define H_HYPERVISOR_DATA 0x60 213 #define H_EOI 0x64 214 #define H_CPPR 0x68 215 #define H_IPI 0x6c 216 #define H_IPOLL 0x70 217 #define H_XIRR 0x74 218 #define H_PERFMON 0x7c 219 #define H_MIGRATE_DMA 0x78 220 #define H_REGISTER_VPA 0xDC 221 #define H_CEDE 0xE0 222 #define H_CONFER 0xE4 223 #define H_PROD 0xE8 224 #define H_GET_PPP 0xEC 225 #define H_SET_PPP 0xF0 226 #define H_PURR 0xF4 227 #define H_PIC 0xF8 228 #define H_REG_CRQ 0xFC 229 #define H_FREE_CRQ 0x100 230 #define H_VIO_SIGNAL 0x104 231 #define H_SEND_CRQ 0x108 232 #define H_COPY_RDMA 0x110 233 #define H_REGISTER_LOGICAL_LAN 0x114 234 #define H_FREE_LOGICAL_LAN 0x118 235 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 236 #define H_SEND_LOGICAL_LAN 0x120 237 #define H_BULK_REMOVE 0x124 238 #define H_MULTICAST_CTRL 0x130 239 #define H_SET_XDABR 0x134 240 #define H_STUFF_TCE 0x138 241 #define H_PUT_TCE_INDIRECT 0x13C 242 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 243 #define H_VTERM_PARTNER_INFO 0x150 244 #define H_REGISTER_VTERM 0x154 245 #define H_FREE_VTERM 0x158 246 #define H_RESET_EVENTS 0x15C 247 #define H_ALLOC_RESOURCE 0x160 248 #define H_FREE_RESOURCE 0x164 249 #define H_MODIFY_QP 0x168 250 #define H_QUERY_QP 0x16C 251 #define H_REREGISTER_PMR 0x170 252 #define H_REGISTER_SMR 0x174 253 #define H_QUERY_MR 0x178 254 #define H_QUERY_MW 0x17C 255 #define H_QUERY_HCA 0x180 256 #define H_QUERY_PORT 0x184 257 #define H_MODIFY_PORT 0x188 258 #define H_DEFINE_AQP1 0x18C 259 #define H_GET_TRACE_BUFFER 0x190 260 #define H_DEFINE_AQP0 0x194 261 #define H_RESIZE_MR 0x198 262 #define H_ATTACH_MCQP 0x19C 263 #define H_DETACH_MCQP 0x1A0 264 #define H_CREATE_RPT 0x1A4 265 #define H_REMOVE_RPT 0x1A8 266 #define H_REGISTER_RPAGES 0x1AC 267 #define H_DISABLE_AND_GETC 0x1B0 268 #define H_ERROR_DATA 0x1B4 269 #define H_GET_HCA_INFO 0x1B8 270 #define H_GET_PERF_COUNT 0x1BC 271 #define H_MANAGE_TRACE 0x1C0 272 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 273 #define H_QUERY_INT_STATE 0x1E4 274 #define H_POLL_PENDING 0x1D8 275 #define H_ILLAN_ATTRIBUTES 0x244 276 #define H_MODIFY_HEA_QP 0x250 277 #define H_QUERY_HEA_QP 0x254 278 #define H_QUERY_HEA 0x258 279 #define H_QUERY_HEA_PORT 0x25C 280 #define H_MODIFY_HEA_PORT 0x260 281 #define H_REG_BCMC 0x264 282 #define H_DEREG_BCMC 0x268 283 #define H_REGISTER_HEA_RPAGES 0x26C 284 #define H_DISABLE_AND_GET_HEA 0x270 285 #define H_GET_HEA_INFO 0x274 286 #define H_ALLOC_HEA_RESOURCE 0x278 287 #define H_ADD_CONN 0x284 288 #define H_DEL_CONN 0x288 289 #define H_JOIN 0x298 290 #define H_VASI_STATE 0x2A4 291 #define H_ENABLE_CRQ 0x2B0 292 #define H_GET_EM_PARMS 0x2B8 293 #define H_SET_MPP 0x2D0 294 #define H_GET_MPP 0x2D4 295 #define H_XIRR_X 0x2FC 296 #define H_SET_MODE 0x31C 297 #define MAX_HCALL_OPCODE H_SET_MODE 298 299 /* The hcalls above are standardized in PAPR and implemented by pHyp 300 * as well. 301 * 302 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 303 * So far we just need one for H_RTAS, but in future we'll need more 304 * for extensions like virtio. We put those into the 0xf000-0xfffc 305 * range which is reserved by PAPR for "platform-specific" hcalls. 306 */ 307 #define KVMPPC_HCALL_BASE 0xf000 308 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 309 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 310 /* Client Architecture support */ 311 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 312 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 313 314 extern sPAPREnvironment *spapr; 315 316 typedef struct sPAPRDeviceTreeUpdateHeader { 317 uint32_t version_id; 318 } sPAPRDeviceTreeUpdateHeader; 319 320 /*#define DEBUG_SPAPR_HCALLS*/ 321 322 #ifdef DEBUG_SPAPR_HCALLS 323 #define hcall_dprintf(fmt, ...) \ 324 do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) 325 #else 326 #define hcall_dprintf(fmt, ...) \ 327 do { } while (0) 328 #endif 329 330 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 331 target_ulong opcode, 332 target_ulong *args); 333 334 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 335 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 336 target_ulong *args); 337 338 int spapr_allocate_irq(int hint, bool lsi); 339 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 340 341 /* RTAS return codes */ 342 #define RTAS_OUT_SUCCESS 0 343 #define RTAS_OUT_NO_ERRORS_FOUND 1 344 #define RTAS_OUT_HW_ERROR -1 345 #define RTAS_OUT_BUSY -2 346 #define RTAS_OUT_PARAM_ERROR -3 347 #define RTAS_OUT_NOT_SUPPORTED -3 348 #define RTAS_OUT_NOT_AUTHORIZED -9002 349 350 /* RTAS tokens */ 351 #define RTAS_TOKEN_BASE 0x2000 352 353 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 354 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 355 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 356 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 357 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 358 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 359 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 360 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 361 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 362 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 363 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 364 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 365 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 366 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 367 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 368 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 369 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 370 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 371 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 372 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 373 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 374 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 375 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 376 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 377 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 378 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 379 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 380 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 381 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 382 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 383 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 384 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 385 386 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x20) 387 388 /* RTAS ibm,get-system-parameter token values */ 389 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 390 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 391 #define RTAS_SYSPARM_UUID 48 392 393 /* Possible values for the platform-processor-diagnostics-run-mode parameter 394 * of the RTAS ibm,get-system-parameter call. 395 */ 396 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 397 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 398 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 399 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 400 401 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 402 { 403 return addr & ~0xF000000000000000ULL; 404 } 405 406 static inline uint32_t rtas_ld(target_ulong phys, int n) 407 { 408 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 409 } 410 411 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 412 { 413 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 414 } 415 416 417 static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, 418 uint8_t *buffer, uint16_t buffer_len) 419 { 420 if (phys_len < 2) { 421 return; 422 } 423 stw_be_phys(&address_space_memory, 424 ppc64_phys_to_real(phys), buffer_len); 425 cpu_physical_memory_write(ppc64_phys_to_real(phys + 2), 426 buffer, MIN(buffer_len, phys_len - 2)); 427 } 428 429 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 430 uint32_t token, 431 uint32_t nargs, target_ulong args, 432 uint32_t nret, target_ulong rets); 433 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 434 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, 435 uint32_t token, uint32_t nargs, target_ulong args, 436 uint32_t nret, target_ulong rets); 437 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 438 hwaddr rtas_size); 439 440 #define SPAPR_TCE_PAGE_SHIFT 12 441 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 442 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 443 444 #define SPAPR_VIO_BASE_LIOBN 0x00000000 445 #define SPAPR_PCI_BASE_LIOBN 0x80000000 446 447 #define RTAS_ERROR_LOG_MAX 2048 448 449 typedef struct sPAPRTCETable sPAPRTCETable; 450 451 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 452 #define SPAPR_TCE_TABLE(obj) \ 453 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 454 455 struct sPAPRTCETable { 456 DeviceState parent; 457 uint32_t liobn; 458 uint32_t nb_table; 459 uint64_t bus_offset; 460 uint32_t page_shift; 461 uint64_t *table; 462 bool bypass; 463 bool vfio_accel; 464 int fd; 465 MemoryRegion iommu; 466 QLIST_ENTRY(sPAPRTCETable) list; 467 }; 468 469 void spapr_events_init(sPAPREnvironment *spapr); 470 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 471 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size); 472 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 473 uint64_t bus_offset, 474 uint32_t page_shift, 475 uint32_t nb_table, 476 bool vfio_accel); 477 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 478 void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass); 479 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 480 uint32_t liobn, uint64_t window, uint32_t size); 481 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 482 sPAPRTCETable *tcet); 483 484 #endif /* !defined (__HW_SPAPR_H__) */ 485