1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 #include "hw/ppc/vof.h" 16 17 struct SpaprVioBus; 18 struct SpaprPhbState; 19 struct SpaprNvram; 20 21 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 22 typedef struct SpaprEventSource SpaprEventSource; 23 typedef struct SpaprPendingHpt SpaprPendingHpt; 24 25 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 26 #define SPAPR_ENTRY_POINT 0x100 27 28 #define SPAPR_TIMEBASE_FREQ 512000000ULL 29 30 #define TYPE_SPAPR_RTC "spapr-rtc" 31 32 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 33 34 struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38 }; 39 40 typedef struct SpaprDimmState SpaprDimmState; 41 42 #define TYPE_SPAPR_MACHINE "spapr-machine" 43 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 44 45 typedef enum { 46 SPAPR_RESIZE_HPT_DEFAULT = 0, 47 SPAPR_RESIZE_HPT_DISABLED, 48 SPAPR_RESIZE_HPT_ENABLED, 49 SPAPR_RESIZE_HPT_REQUIRED, 50 } SpaprResizeHpt; 51 52 /** 53 * Capabilities 54 */ 55 56 /* Hardware Transactional Memory */ 57 #define SPAPR_CAP_HTM 0x00 58 /* Vector Scalar Extensions */ 59 #define SPAPR_CAP_VSX 0x01 60 /* Decimal Floating Point */ 61 #define SPAPR_CAP_DFP 0x02 62 /* Cache Flush on Privilege Change */ 63 #define SPAPR_CAP_CFPC 0x03 64 /* Speculation Barrier Bounds Checking */ 65 #define SPAPR_CAP_SBBC 0x04 66 /* Indirect Branch Serialisation */ 67 #define SPAPR_CAP_IBS 0x05 68 /* HPT Maximum Page Size (encoded as a shift) */ 69 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 70 /* Nested KVM-HV */ 71 #define SPAPR_CAP_NESTED_KVM_HV 0x07 72 /* Large Decrementer */ 73 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 74 /* Count Cache Flush Assist HW Instruction */ 75 #define SPAPR_CAP_CCF_ASSIST 0x09 76 /* Implements PAPR FWNMI option */ 77 #define SPAPR_CAP_FWNMI 0x0A 78 /* Support H_RPT_INVALIDATE */ 79 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 80 /* Num Caps */ 81 #define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1) 82 83 /* 84 * Capability Values 85 */ 86 /* Bool Caps */ 87 #define SPAPR_CAP_OFF 0x00 88 #define SPAPR_CAP_ON 0x01 89 90 /* Custom Caps */ 91 92 /* Generic */ 93 #define SPAPR_CAP_BROKEN 0x00 94 #define SPAPR_CAP_WORKAROUND 0x01 95 #define SPAPR_CAP_FIXED 0x02 96 /* SPAPR_CAP_IBS (cap-ibs) */ 97 #define SPAPR_CAP_FIXED_IBS 0x02 98 #define SPAPR_CAP_FIXED_CCD 0x03 99 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 100 101 #define FDT_MAX_SIZE 0x200000 102 103 /* 104 * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken 105 * from Linux kernel arch/powerpc/mm/numa.h. It represents the 106 * amount of associativity domains for non-CPU resources. 107 * 108 * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 109 * array for any non-CPU resource. 110 * 111 * VCPU_ASSOC_SIZE represents the size of ibm,associativity array 112 * for CPUs, which has an extra element (vcpu_id) in the end. 113 */ 114 #define MAX_DISTANCE_REF_POINTS 4 115 #define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1) 116 #define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1) 117 118 /* Max number of these GPUsper a physical box */ 119 #define NVGPU_MAX_NUM 6 120 121 typedef struct SpaprCapabilities SpaprCapabilities; 122 struct SpaprCapabilities { 123 uint8_t caps[SPAPR_CAP_NUM]; 124 }; 125 126 /** 127 * SpaprMachineClass: 128 */ 129 struct SpaprMachineClass { 130 /*< private >*/ 131 MachineClass parent_class; 132 133 /*< public >*/ 134 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 135 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 136 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 137 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 138 bool pre_2_10_has_unused_icps; 139 bool legacy_irq_allocation; 140 uint32_t nr_xirqs; 141 bool broken_host_serial_model; /* present real host info to the guest */ 142 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 143 bool linux_pci_probe; 144 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 145 hwaddr rma_limit; /* clamp the RMA to this size */ 146 bool pre_5_1_assoc_refpoints; 147 bool pre_5_2_numa_associativity; 148 149 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 150 uint64_t *buid, hwaddr *pio, 151 hwaddr *mmio32, hwaddr *mmio64, 152 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 153 hwaddr *nv2atsd, Error **errp); 154 SpaprResizeHpt resize_hpt_default; 155 SpaprCapabilities default_caps; 156 SpaprIrq *irq; 157 }; 158 159 /** 160 * SpaprMachineState: 161 */ 162 struct SpaprMachineState { 163 /*< private >*/ 164 MachineState parent_obj; 165 166 struct SpaprVioBus *vio_bus; 167 QLIST_HEAD(, SpaprPhbState) phbs; 168 struct SpaprNvram *nvram; 169 SpaprRtcState rtc; 170 171 SpaprResizeHpt resize_hpt; 172 void *htab; 173 uint32_t htab_shift; 174 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 175 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 176 177 hwaddr rma_size; 178 uint32_t fdt_size; 179 uint32_t fdt_initial_size; 180 void *fdt_blob; 181 long kernel_size; 182 bool kernel_le; 183 uint64_t kernel_addr; 184 uint32_t initrd_base; 185 long initrd_size; 186 Vof *vof; 187 uint64_t rtc_offset; /* Now used only during incoming migration */ 188 struct PPCTimebase tb; 189 bool has_graphics; 190 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 191 192 Notifier epow_notifier; 193 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 194 bool use_hotplug_event_source; 195 SpaprEventSource *event_sources; 196 197 /* ibm,client-architecture-support option negotiation */ 198 bool cas_pre_isa3_guest; 199 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 200 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 201 uint32_t max_compat_pvr; 202 203 /* Migration state */ 204 int htab_save_index; 205 bool htab_first_pass; 206 int htab_fd; 207 208 /* Pending DIMM unplug cache. It is populated when a LMB 209 * unplug starts. It can be regenerated if a migration 210 * occurs during the unplug process. */ 211 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 212 213 /* State related to FWNMI option */ 214 215 /* System Reset and Machine Check Notification Routine addresses 216 * registered by "ibm,nmi-register" RTAS call. 217 */ 218 target_ulong fwnmi_system_reset_addr; 219 target_ulong fwnmi_machine_check_addr; 220 221 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 222 * set to -1 if a FWNMI machine check is not in progress, else is set to 223 * the CPU that was delivered the machine check, and is set back to -1 224 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 225 * to synchronize other CPUs. 226 */ 227 int fwnmi_machine_check_interlock; 228 QemuCond fwnmi_machine_check_interlock_cond; 229 230 /* Set by -boot */ 231 char *boot_device; 232 233 /*< public >*/ 234 char *kvm_type; 235 char *host_model; 236 char *host_serial; 237 238 int32_t irq_map_nr; 239 unsigned long *irq_map; 240 SpaprIrq *irq; 241 qemu_irq *qirqs; 242 SpaprInterruptController *active_intc; 243 ICSState *ics; 244 SpaprXive *xive; 245 246 bool cmd_line_caps[SPAPR_CAP_NUM]; 247 SpaprCapabilities def, eff, mig; 248 249 unsigned gpu_numa_id; 250 SpaprTpmProxy *tpm_proxy; 251 252 uint32_t numa_assoc_array[MAX_NODES + NVGPU_MAX_NUM][NUMA_ASSOC_SIZE]; 253 254 Error *fwnmi_migration_blocker; 255 }; 256 257 #define H_SUCCESS 0 258 #define H_BUSY 1 /* Hardware busy -- retry later */ 259 #define H_CLOSED 2 /* Resource closed */ 260 #define H_NOT_AVAILABLE 3 261 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 262 #define H_PARTIAL 5 263 #define H_IN_PROGRESS 14 /* Kind of like busy */ 264 #define H_PAGE_REGISTERED 15 265 #define H_PARTIAL_STORE 16 266 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 267 #define H_CONTINUE 18 /* Returned from H_Join on success */ 268 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 269 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 270 is a good time to retry */ 271 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 272 is a good time to retry */ 273 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 274 is a good time to retry */ 275 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 276 is a good time to retry */ 277 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 278 is a good time to retry */ 279 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 280 is a good time to retry */ 281 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 282 #define H_HARDWARE -1 /* Hardware error */ 283 #define H_FUNCTION -2 /* Function not supported */ 284 #define H_PRIVILEGE -3 /* Caller not privileged */ 285 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 286 #define H_BAD_MODE -5 /* Illegal msr value */ 287 #define H_PTEG_FULL -6 /* PTEG is full */ 288 #define H_NOT_FOUND -7 /* PTE was not found" */ 289 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 290 #define H_NO_MEM -9 291 #define H_AUTHORITY -10 292 #define H_PERMISSION -11 293 #define H_DROPPED -12 294 #define H_SOURCE_PARM -13 295 #define H_DEST_PARM -14 296 #define H_REMOTE_PARM -15 297 #define H_RESOURCE -16 298 #define H_ADAPTER_PARM -17 299 #define H_RH_PARM -18 300 #define H_RCQ_PARM -19 301 #define H_SCQ_PARM -20 302 #define H_EQ_PARM -21 303 #define H_RT_PARM -22 304 #define H_ST_PARM -23 305 #define H_SIGT_PARM -24 306 #define H_TOKEN_PARM -25 307 #define H_MLENGTH_PARM -27 308 #define H_MEM_PARM -28 309 #define H_MEM_ACCESS_PARM -29 310 #define H_ATTR_PARM -30 311 #define H_PORT_PARM -31 312 #define H_MCG_PARM -32 313 #define H_VL_PARM -33 314 #define H_TSIZE_PARM -34 315 #define H_TRACE_PARM -35 316 317 #define H_MASK_PARM -37 318 #define H_MCG_FULL -38 319 #define H_ALIAS_EXIST -39 320 #define H_P_COUNTER -40 321 #define H_TABLE_FULL -41 322 #define H_ALT_TABLE -42 323 #define H_MR_CONDITION -43 324 #define H_NOT_ENOUGH_RESOURCES -44 325 #define H_R_STATE -45 326 #define H_RESCINDEND -46 327 #define H_P2 -55 328 #define H_P3 -56 329 #define H_P4 -57 330 #define H_P5 -58 331 #define H_P6 -59 332 #define H_P7 -60 333 #define H_P8 -61 334 #define H_P9 -62 335 #define H_OVERLAP -68 336 #define H_UNSUPPORTED_FLAG -256 337 #define H_MULTI_THREADS_ACTIVE -9005 338 339 340 /* Long Busy is a condition that can be returned by the firmware 341 * when a call cannot be completed now, but the identical call 342 * should be retried later. This prevents calls blocking in the 343 * firmware for long periods of time. Annoyingly the firmware can return 344 * a range of return codes, hinting at how long we should wait before 345 * retrying. If you don't care for the hint, the macro below is a good 346 * way to check for the long_busy return codes 347 */ 348 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 349 && (x <= H_LONG_BUSY_END_RANGE)) 350 351 /* Flags */ 352 #define H_LARGE_PAGE (1ULL<<(63-16)) 353 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 354 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 355 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 356 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 357 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 358 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 359 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 360 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 361 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 362 #define H_ANDCOND (1ULL<<(63-33)) 363 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 364 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 365 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 366 #define H_COPY_PAGE (1ULL<<(63-49)) 367 #define H_N (1ULL<<(63-61)) 368 #define H_PP1 (1ULL<<(63-62)) 369 #define H_PP2 (1ULL<<(63-63)) 370 371 /* Values for 2nd argument to H_SET_MODE */ 372 #define H_SET_MODE_RESOURCE_SET_CIABR 1 373 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 374 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 375 #define H_SET_MODE_RESOURCE_LE 4 376 377 /* Flags for H_SET_MODE_RESOURCE_LE */ 378 #define H_SET_MODE_ENDIAN_BIG 0 379 #define H_SET_MODE_ENDIAN_LITTLE 1 380 381 /* VASI States */ 382 #define H_VASI_INVALID 0 383 #define H_VASI_ENABLED 1 384 #define H_VASI_ABORTED 2 385 #define H_VASI_SUSPENDING 3 386 #define H_VASI_SUSPENDED 4 387 #define H_VASI_RESUMED 5 388 #define H_VASI_COMPLETED 6 389 390 /* DABRX flags */ 391 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 392 #define H_DABRX_KERNEL (1ULL<<(63-62)) 393 #define H_DABRX_USER (1ULL<<(63-63)) 394 395 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 396 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 397 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 398 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 399 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 400 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 401 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 402 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 403 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 404 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 405 406 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 407 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 408 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 409 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 410 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 411 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 412 413 /* Each control block has to be on a 4K boundary */ 414 #define H_CB_ALIGNMENT 4096 415 416 /* pSeries hypervisor opcodes */ 417 #define H_REMOVE 0x04 418 #define H_ENTER 0x08 419 #define H_READ 0x0c 420 #define H_CLEAR_MOD 0x10 421 #define H_CLEAR_REF 0x14 422 #define H_PROTECT 0x18 423 #define H_GET_TCE 0x1c 424 #define H_PUT_TCE 0x20 425 #define H_SET_SPRG0 0x24 426 #define H_SET_DABR 0x28 427 #define H_PAGE_INIT 0x2c 428 #define H_SET_ASR 0x30 429 #define H_ASR_ON 0x34 430 #define H_ASR_OFF 0x38 431 #define H_LOGICAL_CI_LOAD 0x3c 432 #define H_LOGICAL_CI_STORE 0x40 433 #define H_LOGICAL_CACHE_LOAD 0x44 434 #define H_LOGICAL_CACHE_STORE 0x48 435 #define H_LOGICAL_ICBI 0x4c 436 #define H_LOGICAL_DCBF 0x50 437 #define H_GET_TERM_CHAR 0x54 438 #define H_PUT_TERM_CHAR 0x58 439 #define H_REAL_TO_LOGICAL 0x5c 440 #define H_HYPERVISOR_DATA 0x60 441 #define H_EOI 0x64 442 #define H_CPPR 0x68 443 #define H_IPI 0x6c 444 #define H_IPOLL 0x70 445 #define H_XIRR 0x74 446 #define H_PERFMON 0x7c 447 #define H_MIGRATE_DMA 0x78 448 #define H_REGISTER_VPA 0xDC 449 #define H_CEDE 0xE0 450 #define H_CONFER 0xE4 451 #define H_PROD 0xE8 452 #define H_GET_PPP 0xEC 453 #define H_SET_PPP 0xF0 454 #define H_PURR 0xF4 455 #define H_PIC 0xF8 456 #define H_REG_CRQ 0xFC 457 #define H_FREE_CRQ 0x100 458 #define H_VIO_SIGNAL 0x104 459 #define H_SEND_CRQ 0x108 460 #define H_COPY_RDMA 0x110 461 #define H_REGISTER_LOGICAL_LAN 0x114 462 #define H_FREE_LOGICAL_LAN 0x118 463 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 464 #define H_SEND_LOGICAL_LAN 0x120 465 #define H_BULK_REMOVE 0x124 466 #define H_MULTICAST_CTRL 0x130 467 #define H_SET_XDABR 0x134 468 #define H_STUFF_TCE 0x138 469 #define H_PUT_TCE_INDIRECT 0x13C 470 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 471 #define H_VTERM_PARTNER_INFO 0x150 472 #define H_REGISTER_VTERM 0x154 473 #define H_FREE_VTERM 0x158 474 #define H_RESET_EVENTS 0x15C 475 #define H_ALLOC_RESOURCE 0x160 476 #define H_FREE_RESOURCE 0x164 477 #define H_MODIFY_QP 0x168 478 #define H_QUERY_QP 0x16C 479 #define H_REREGISTER_PMR 0x170 480 #define H_REGISTER_SMR 0x174 481 #define H_QUERY_MR 0x178 482 #define H_QUERY_MW 0x17C 483 #define H_QUERY_HCA 0x180 484 #define H_QUERY_PORT 0x184 485 #define H_MODIFY_PORT 0x188 486 #define H_DEFINE_AQP1 0x18C 487 #define H_GET_TRACE_BUFFER 0x190 488 #define H_DEFINE_AQP0 0x194 489 #define H_RESIZE_MR 0x198 490 #define H_ATTACH_MCQP 0x19C 491 #define H_DETACH_MCQP 0x1A0 492 #define H_CREATE_RPT 0x1A4 493 #define H_REMOVE_RPT 0x1A8 494 #define H_REGISTER_RPAGES 0x1AC 495 #define H_DISABLE_AND_GETC 0x1B0 496 #define H_ERROR_DATA 0x1B4 497 #define H_GET_HCA_INFO 0x1B8 498 #define H_GET_PERF_COUNT 0x1BC 499 #define H_MANAGE_TRACE 0x1C0 500 #define H_GET_CPU_CHARACTERISTICS 0x1C8 501 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 502 #define H_QUERY_INT_STATE 0x1E4 503 #define H_POLL_PENDING 0x1D8 504 #define H_ILLAN_ATTRIBUTES 0x244 505 #define H_MODIFY_HEA_QP 0x250 506 #define H_QUERY_HEA_QP 0x254 507 #define H_QUERY_HEA 0x258 508 #define H_QUERY_HEA_PORT 0x25C 509 #define H_MODIFY_HEA_PORT 0x260 510 #define H_REG_BCMC 0x264 511 #define H_DEREG_BCMC 0x268 512 #define H_REGISTER_HEA_RPAGES 0x26C 513 #define H_DISABLE_AND_GET_HEA 0x270 514 #define H_GET_HEA_INFO 0x274 515 #define H_ALLOC_HEA_RESOURCE 0x278 516 #define H_ADD_CONN 0x284 517 #define H_DEL_CONN 0x288 518 #define H_JOIN 0x298 519 #define H_VASI_STATE 0x2A4 520 #define H_ENABLE_CRQ 0x2B0 521 #define H_GET_EM_PARMS 0x2B8 522 #define H_SET_MPP 0x2D0 523 #define H_GET_MPP 0x2D4 524 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 525 #define H_XIRR_X 0x2FC 526 #define H_RANDOM 0x300 527 #define H_SET_MODE 0x31C 528 #define H_RESIZE_HPT_PREPARE 0x36C 529 #define H_RESIZE_HPT_COMMIT 0x370 530 #define H_CLEAN_SLB 0x374 531 #define H_INVALIDATE_PID 0x378 532 #define H_REGISTER_PROC_TBL 0x37C 533 #define H_SIGNAL_SYS_RESET 0x380 534 535 #define H_INT_GET_SOURCE_INFO 0x3A8 536 #define H_INT_SET_SOURCE_CONFIG 0x3AC 537 #define H_INT_GET_SOURCE_CONFIG 0x3B0 538 #define H_INT_GET_QUEUE_INFO 0x3B4 539 #define H_INT_SET_QUEUE_CONFIG 0x3B8 540 #define H_INT_GET_QUEUE_CONFIG 0x3BC 541 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 542 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 543 #define H_INT_ESB 0x3C8 544 #define H_INT_SYNC 0x3CC 545 #define H_INT_RESET 0x3D0 546 #define H_SCM_READ_METADATA 0x3E4 547 #define H_SCM_WRITE_METADATA 0x3E8 548 #define H_SCM_BIND_MEM 0x3EC 549 #define H_SCM_UNBIND_MEM 0x3F0 550 #define H_SCM_UNBIND_ALL 0x3FC 551 #define H_SCM_HEALTH 0x400 552 #define H_RPT_INVALIDATE 0x448 553 554 #define MAX_HCALL_OPCODE H_RPT_INVALIDATE 555 556 /* The hcalls above are standardized in PAPR and implemented by pHyp 557 * as well. 558 * 559 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 560 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 561 * for "platform-specific" hcalls. 562 */ 563 #define KVMPPC_HCALL_BASE 0xf000 564 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 565 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 566 /* Client Architecture support */ 567 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 568 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 569 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 570 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 571 #define KVMPPC_HCALL_MAX KVMPPC_H_VOF_CLIENT 572 573 /* 574 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 575 * Secure VM mode via an Ultravisor / Protected Execution Facility 576 */ 577 #define SVM_HCALL_BASE 0xEF00 578 #define SVM_H_TPM_COMM 0xEF10 579 #define SVM_HCALL_MAX SVM_H_TPM_COMM 580 581 582 typedef struct SpaprDeviceTreeUpdateHeader { 583 uint32_t version_id; 584 } SpaprDeviceTreeUpdateHeader; 585 586 #define hcall_dprintf(fmt, ...) \ 587 do { \ 588 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 589 } while (0) 590 591 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 592 target_ulong opcode, 593 target_ulong *args); 594 595 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 596 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 597 target_ulong *args); 598 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 599 target_ulong shift); 600 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 601 target_ulong flags, target_ulong shift); 602 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 603 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 604 605 /* Virtual Processor Area structure constants */ 606 #define VPA_MIN_SIZE 640 607 #define VPA_SIZE_OFFSET 0x4 608 #define VPA_SHARED_PROC_OFFSET 0x9 609 #define VPA_SHARED_PROC_VAL 0x2 610 #define VPA_DISPATCH_COUNTER 0x100 611 612 /* ibm,set-eeh-option */ 613 #define RTAS_EEH_DISABLE 0 614 #define RTAS_EEH_ENABLE 1 615 #define RTAS_EEH_THAW_IO 2 616 #define RTAS_EEH_THAW_DMA 3 617 618 /* ibm,get-config-addr-info2 */ 619 #define RTAS_GET_PE_ADDR 0 620 #define RTAS_GET_PE_MODE 1 621 #define RTAS_PE_MODE_NONE 0 622 #define RTAS_PE_MODE_NOT_SHARED 1 623 #define RTAS_PE_MODE_SHARED 2 624 625 /* ibm,read-slot-reset-state2 */ 626 #define RTAS_EEH_PE_STATE_NORMAL 0 627 #define RTAS_EEH_PE_STATE_RESET 1 628 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 629 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 630 #define RTAS_EEH_PE_STATE_UNAVAIL 5 631 #define RTAS_EEH_NOT_SUPPORT 0 632 #define RTAS_EEH_SUPPORT 1 633 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 634 #define RTAS_EEH_PE_RECOVER_INFO 0 635 636 /* ibm,set-slot-reset */ 637 #define RTAS_SLOT_RESET_DEACTIVATE 0 638 #define RTAS_SLOT_RESET_HOT 1 639 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 640 641 /* ibm,slot-error-detail */ 642 #define RTAS_SLOT_TEMP_ERR_LOG 1 643 #define RTAS_SLOT_PERM_ERR_LOG 2 644 645 /* RTAS return codes */ 646 #define RTAS_OUT_SUCCESS 0 647 #define RTAS_OUT_NO_ERRORS_FOUND 1 648 #define RTAS_OUT_HW_ERROR -1 649 #define RTAS_OUT_BUSY -2 650 #define RTAS_OUT_PARAM_ERROR -3 651 #define RTAS_OUT_NOT_SUPPORTED -3 652 #define RTAS_OUT_NO_SUCH_INDICATOR -3 653 #define RTAS_OUT_NOT_AUTHORIZED -9002 654 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 655 656 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 657 #define RTAS_DDW_PGSIZE_4K 0x01 658 #define RTAS_DDW_PGSIZE_64K 0x02 659 #define RTAS_DDW_PGSIZE_16M 0x04 660 #define RTAS_DDW_PGSIZE_32M 0x08 661 #define RTAS_DDW_PGSIZE_64M 0x10 662 #define RTAS_DDW_PGSIZE_128M 0x20 663 #define RTAS_DDW_PGSIZE_256M 0x40 664 #define RTAS_DDW_PGSIZE_16G 0x80 665 666 /* RTAS tokens */ 667 #define RTAS_TOKEN_BASE 0x2000 668 669 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 670 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 671 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 672 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 673 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 674 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 675 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 676 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 677 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 678 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 679 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 680 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 681 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 682 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 683 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 684 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 685 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 686 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 687 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 688 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 689 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 690 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 691 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 692 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 693 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 694 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 695 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 696 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 697 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 698 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 699 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 700 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 701 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 702 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 703 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 704 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 705 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 706 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 707 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 708 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 709 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 710 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 711 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 712 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 713 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 714 715 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 716 717 /* RTAS ibm,get-system-parameter token values */ 718 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 719 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 720 #define RTAS_SYSPARM_UUID 48 721 722 /* RTAS indicator/sensor types 723 * 724 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 725 * 726 * NOTE: currently only DR-related sensors are implemented here 727 */ 728 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 729 #define RTAS_SENSOR_TYPE_DR 9002 730 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 731 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 732 733 /* Possible values for the platform-processor-diagnostics-run-mode parameter 734 * of the RTAS ibm,get-system-parameter call. 735 */ 736 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 737 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 738 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 739 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 740 741 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 742 { 743 return addr & ~0xF000000000000000ULL; 744 } 745 746 static inline uint32_t rtas_ld(target_ulong phys, int n) 747 { 748 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 749 } 750 751 static inline uint64_t rtas_ldq(target_ulong phys, int n) 752 { 753 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 754 } 755 756 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 757 { 758 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 759 } 760 761 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 762 uint32_t token, 763 uint32_t nargs, target_ulong args, 764 uint32_t nret, target_ulong rets); 765 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 766 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 767 uint32_t token, uint32_t nargs, target_ulong args, 768 uint32_t nret, target_ulong rets); 769 void spapr_dt_rtas_tokens(void *fdt, int rtas); 770 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 771 772 #define SPAPR_TCE_PAGE_SHIFT 12 773 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 774 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 775 776 #define SPAPR_VIO_BASE_LIOBN 0x00000000 777 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 778 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 779 (0x80000000 | ((phb_index) << 8) | (window_num)) 780 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 781 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 782 783 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 784 #define RTAS_ERROR_LOG_MAX 2048 785 786 /* Offset from rtas-base where error log is placed */ 787 #define RTAS_ERROR_LOG_OFFSET 0x30 788 789 #define RTAS_EVENT_SCAN_RATE 1 790 791 /* This helper should be used to encode interrupt specifiers when the related 792 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 793 * VIO devices, RTAS event sources and PHBs). 794 */ 795 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 796 { 797 intspec[0] = cpu_to_be32(irq); 798 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 799 } 800 801 802 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 803 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 804 805 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 806 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 807 TYPE_SPAPR_IOMMU_MEMORY_REGION) 808 809 struct SpaprTceTable { 810 DeviceState parent; 811 uint32_t liobn; 812 uint32_t nb_table; 813 uint64_t bus_offset; 814 uint32_t page_shift; 815 uint64_t *table; 816 uint32_t mig_nb_table; 817 uint64_t *mig_table; 818 bool bypass; 819 bool need_vfio; 820 bool skipping_replay; 821 int fd; 822 MemoryRegion root; 823 IOMMUMemoryRegion iommu; 824 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 825 QLIST_ENTRY(SpaprTceTable) list; 826 }; 827 828 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 829 830 struct SpaprEventLogEntry { 831 uint32_t summary; 832 uint32_t extended_length; 833 void *extended_log; 834 QTAILQ_ENTRY(SpaprEventLogEntry) next; 835 }; 836 837 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 838 void spapr_events_init(SpaprMachineState *sm); 839 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 840 void close_htab_fd(SpaprMachineState *spapr); 841 void spapr_setup_hpt(SpaprMachineState *spapr); 842 void spapr_free_hpt(SpaprMachineState *spapr); 843 void spapr_check_mmu_mode(bool guest_radix); 844 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 845 void spapr_tce_table_enable(SpaprTceTable *tcet, 846 uint32_t page_shift, uint64_t bus_offset, 847 uint32_t nb_table); 848 void spapr_tce_table_disable(SpaprTceTable *tcet); 849 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 850 851 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 852 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 853 uint32_t liobn, uint64_t window, uint32_t size); 854 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 855 SpaprTceTable *tcet); 856 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 857 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 858 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 859 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 860 uint32_t count); 861 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 862 uint32_t count); 863 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 864 uint32_t count, uint32_t index); 865 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 866 uint32_t count, uint32_t index); 867 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 868 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 869 void spapr_clear_pending_events(SpaprMachineState *spapr); 870 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 871 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 872 int spapr_max_server_number(SpaprMachineState *spapr); 873 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 874 uint64_t pte0, uint64_t pte1); 875 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 876 877 /* DRC callbacks. */ 878 void spapr_core_release(DeviceState *dev); 879 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 880 void *fdt, int *fdt_start_offset, Error **errp); 881 void spapr_lmb_release(DeviceState *dev); 882 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 883 void *fdt, int *fdt_start_offset, Error **errp); 884 void spapr_phb_release(DeviceState *dev); 885 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 886 void *fdt, int *fdt_start_offset, Error **errp); 887 888 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 889 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 890 891 #define TYPE_SPAPR_RNG "spapr-rng" 892 893 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 894 895 /* 896 * This defines the maximum number of DIMM slots we can have for sPAPR 897 * guest. This is not defined by sPAPR but we are defining it to 32 slots 898 * based on default number of slots provided by PowerPC kernel. 899 */ 900 #define SPAPR_MAX_RAM_SLOTS 32 901 902 /* 1GB alignment for hotplug memory region */ 903 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 904 905 /* 906 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 907 * property under ibm,dynamic-reconfiguration-memory node. 908 */ 909 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 910 911 /* 912 * Defines for flag value in ibm,dynamic-memory property under 913 * ibm,dynamic-reconfiguration-memory node. 914 */ 915 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 916 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 917 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 918 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 919 920 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 921 922 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 923 924 int spapr_get_vcpu_id(PowerPCCPU *cpu); 925 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 926 PowerPCCPU *spapr_find_cpu(int vcpu_id); 927 928 int spapr_caps_pre_load(void *opaque); 929 int spapr_caps_pre_save(void *opaque); 930 931 /* 932 * Handling of optional capabilities 933 */ 934 extern const VMStateDescription vmstate_spapr_cap_htm; 935 extern const VMStateDescription vmstate_spapr_cap_vsx; 936 extern const VMStateDescription vmstate_spapr_cap_dfp; 937 extern const VMStateDescription vmstate_spapr_cap_cfpc; 938 extern const VMStateDescription vmstate_spapr_cap_sbbc; 939 extern const VMStateDescription vmstate_spapr_cap_ibs; 940 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 941 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 942 extern const VMStateDescription vmstate_spapr_cap_large_decr; 943 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 944 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 945 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 946 947 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 948 { 949 return spapr->eff.caps[cap]; 950 } 951 952 void spapr_caps_init(SpaprMachineState *spapr); 953 void spapr_caps_apply(SpaprMachineState *spapr); 954 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 955 void spapr_caps_add_properties(SpaprMachineClass *smc); 956 int spapr_caps_post_migration(SpaprMachineState *spapr); 957 958 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 959 Error **errp); 960 /* 961 * XIVE definitions 962 */ 963 #define SPAPR_OV5_XIVE_LEGACY 0x0 964 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 965 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 966 967 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 968 hwaddr spapr_get_rtas_addr(void); 969 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 970 971 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 972 void spapr_vof_quiesce(MachineState *ms); 973 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 974 void *val, int vallen); 975 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 976 target_ulong opcode, target_ulong *args); 977 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 978 CPUState *cs, 979 target_ulong ovec_addr); 980 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 981 982 #endif /* HW_SPAPR_H */ 983