1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 16 struct SpaprVioBus; 17 struct SpaprPhbState; 18 struct SpaprNvram; 19 20 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21 typedef struct SpaprEventSource SpaprEventSource; 22 typedef struct SpaprPendingHpt SpaprPendingHpt; 23 24 typedef struct Vof Vof; 25 26 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 27 #define SPAPR_ENTRY_POINT 0x100 28 29 #define SPAPR_TIMEBASE_FREQ 512000000ULL 30 31 #define TYPE_SPAPR_RTC "spapr-rtc" 32 33 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 34 35 struct SpaprRtcState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 int64_t ns_offset; 39 }; 40 41 typedef struct SpaprDimmState SpaprDimmState; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } SpaprResizeHpt; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x00 59 /* Vector Scalar Extensions */ 60 #define SPAPR_CAP_VSX 0x01 61 /* Decimal Floating Point */ 62 #define SPAPR_CAP_DFP 0x02 63 /* Cache Flush on Privilege Change */ 64 #define SPAPR_CAP_CFPC 0x03 65 /* Speculation Barrier Bounds Checking */ 66 #define SPAPR_CAP_SBBC 0x04 67 /* Indirect Branch Serialisation */ 68 #define SPAPR_CAP_IBS 0x05 69 /* HPT Maximum Page Size (encoded as a shift) */ 70 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 71 /* Nested KVM-HV */ 72 #define SPAPR_CAP_NESTED_KVM_HV 0x07 73 /* Large Decrementer */ 74 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 75 /* Count Cache Flush Assist HW Instruction */ 76 #define SPAPR_CAP_CCF_ASSIST 0x09 77 /* Implements PAPR FWNMI option */ 78 #define SPAPR_CAP_FWNMI 0x0A 79 /* Support H_RPT_INVALIDATE */ 80 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 81 /* Num Caps */ 82 #define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1) 83 84 /* 85 * Capability Values 86 */ 87 /* Bool Caps */ 88 #define SPAPR_CAP_OFF 0x00 89 #define SPAPR_CAP_ON 0x01 90 91 /* Custom Caps */ 92 93 /* Generic */ 94 #define SPAPR_CAP_BROKEN 0x00 95 #define SPAPR_CAP_WORKAROUND 0x01 96 #define SPAPR_CAP_FIXED 0x02 97 /* SPAPR_CAP_IBS (cap-ibs) */ 98 #define SPAPR_CAP_FIXED_IBS 0x02 99 #define SPAPR_CAP_FIXED_CCD 0x03 100 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 101 102 #define FDT_MAX_SIZE 0x200000 103 104 /* Max number of GPUs per system */ 105 #define NVGPU_MAX_NUM 6 106 107 /* Max number of NUMA nodes */ 108 #define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM) 109 110 /* 111 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 112 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 113 * kernel source. It represents the amount of associativity domains 114 * for non-CPU resources. 115 * 116 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 117 * array for any non-CPU resource. 118 */ 119 #define FORM1_DIST_REF_POINTS 4 120 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 121 122 /* 123 * FORM2 NUMA affinity has a single associativity domain, giving 124 * us a assoc size of 2. 125 */ 126 #define FORM2_DIST_REF_POINTS 1 127 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 128 129 typedef struct SpaprCapabilities SpaprCapabilities; 130 struct SpaprCapabilities { 131 uint8_t caps[SPAPR_CAP_NUM]; 132 }; 133 134 /** 135 * SpaprMachineClass: 136 */ 137 struct SpaprMachineClass { 138 /*< private >*/ 139 MachineClass parent_class; 140 141 /*< public >*/ 142 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 143 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 144 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 145 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 146 bool pre_2_10_has_unused_icps; 147 bool legacy_irq_allocation; 148 uint32_t nr_xirqs; 149 bool broken_host_serial_model; /* present real host info to the guest */ 150 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 151 bool linux_pci_probe; 152 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 153 hwaddr rma_limit; /* clamp the RMA to this size */ 154 bool pre_5_1_assoc_refpoints; 155 bool pre_5_2_numa_associativity; 156 bool pre_6_2_numa_affinity; 157 158 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 159 uint64_t *buid, hwaddr *pio, 160 hwaddr *mmio32, hwaddr *mmio64, 161 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 162 hwaddr *nv2atsd, Error **errp); 163 SpaprResizeHpt resize_hpt_default; 164 SpaprCapabilities default_caps; 165 SpaprIrq *irq; 166 }; 167 168 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 169 170 #define TYPE_SPAPR_WDT "spapr-wdt" 171 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 172 173 typedef struct SpaprWatchdog { 174 /*< private >*/ 175 DeviceState parent_obj; 176 /*< public >*/ 177 178 QEMUTimer timer; 179 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 180 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 181 } SpaprWatchdog; 182 183 /** 184 * SpaprMachineState: 185 */ 186 struct SpaprMachineState { 187 /*< private >*/ 188 MachineState parent_obj; 189 190 struct SpaprVioBus *vio_bus; 191 QLIST_HEAD(, SpaprPhbState) phbs; 192 struct SpaprNvram *nvram; 193 SpaprRtcState rtc; 194 195 SpaprResizeHpt resize_hpt; 196 void *htab; 197 uint32_t htab_shift; 198 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 199 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 200 201 hwaddr rma_size; 202 uint32_t fdt_size; 203 uint32_t fdt_initial_size; 204 void *fdt_blob; 205 long kernel_size; 206 bool kernel_le; 207 uint64_t kernel_addr; 208 uint32_t initrd_base; 209 long initrd_size; 210 Vof *vof; 211 uint64_t rtc_offset; /* Now used only during incoming migration */ 212 struct PPCTimebase tb; 213 bool want_stdout_path; 214 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 215 216 /* Nested HV support (TCG only) */ 217 uint64_t nested_ptcr; 218 219 Notifier epow_notifier; 220 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 221 bool use_hotplug_event_source; 222 SpaprEventSource *event_sources; 223 224 /* ibm,client-architecture-support option negotiation */ 225 bool cas_pre_isa3_guest; 226 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 227 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 228 uint32_t max_compat_pvr; 229 230 /* Migration state */ 231 int htab_save_index; 232 bool htab_first_pass; 233 int htab_fd; 234 235 /* Pending DIMM unplug cache. It is populated when a LMB 236 * unplug starts. It can be regenerated if a migration 237 * occurs during the unplug process. */ 238 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 239 240 /* State related to FWNMI option */ 241 242 /* System Reset and Machine Check Notification Routine addresses 243 * registered by "ibm,nmi-register" RTAS call. 244 */ 245 target_ulong fwnmi_system_reset_addr; 246 target_ulong fwnmi_machine_check_addr; 247 248 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 249 * set to -1 if a FWNMI machine check is not in progress, else is set to 250 * the CPU that was delivered the machine check, and is set back to -1 251 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 252 * to synchronize other CPUs. 253 */ 254 int fwnmi_machine_check_interlock; 255 QemuCond fwnmi_machine_check_interlock_cond; 256 257 /* Set by -boot */ 258 char *boot_device; 259 260 /*< public >*/ 261 char *kvm_type; 262 char *host_model; 263 char *host_serial; 264 265 int32_t irq_map_nr; 266 unsigned long *irq_map; 267 SpaprIrq *irq; 268 qemu_irq *qirqs; 269 SpaprInterruptController *active_intc; 270 ICSState *ics; 271 SpaprXive *xive; 272 273 bool cmd_line_caps[SPAPR_CAP_NUM]; 274 SpaprCapabilities def, eff, mig; 275 276 unsigned gpu_numa_id; 277 SpaprTpmProxy *tpm_proxy; 278 279 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 280 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 281 282 Error *fwnmi_migration_blocker; 283 284 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 285 }; 286 287 #define H_SUCCESS 0 288 #define H_BUSY 1 /* Hardware busy -- retry later */ 289 #define H_CLOSED 2 /* Resource closed */ 290 #define H_NOT_AVAILABLE 3 291 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 292 #define H_PARTIAL 5 293 #define H_IN_PROGRESS 14 /* Kind of like busy */ 294 #define H_PAGE_REGISTERED 15 295 #define H_PARTIAL_STORE 16 296 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 297 #define H_CONTINUE 18 /* Returned from H_Join on success */ 298 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 299 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 300 is a good time to retry */ 301 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 302 is a good time to retry */ 303 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 304 is a good time to retry */ 305 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 306 is a good time to retry */ 307 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 308 is a good time to retry */ 309 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 310 is a good time to retry */ 311 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 312 #define H_HARDWARE -1 /* Hardware error */ 313 #define H_FUNCTION -2 /* Function not supported */ 314 #define H_PRIVILEGE -3 /* Caller not privileged */ 315 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 316 #define H_BAD_MODE -5 /* Illegal msr value */ 317 #define H_PTEG_FULL -6 /* PTEG is full */ 318 #define H_NOT_FOUND -7 /* PTE was not found" */ 319 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 320 #define H_NO_MEM -9 321 #define H_AUTHORITY -10 322 #define H_PERMISSION -11 323 #define H_DROPPED -12 324 #define H_SOURCE_PARM -13 325 #define H_DEST_PARM -14 326 #define H_REMOTE_PARM -15 327 #define H_RESOURCE -16 328 #define H_ADAPTER_PARM -17 329 #define H_RH_PARM -18 330 #define H_RCQ_PARM -19 331 #define H_SCQ_PARM -20 332 #define H_EQ_PARM -21 333 #define H_RT_PARM -22 334 #define H_ST_PARM -23 335 #define H_SIGT_PARM -24 336 #define H_TOKEN_PARM -25 337 #define H_MLENGTH_PARM -27 338 #define H_MEM_PARM -28 339 #define H_MEM_ACCESS_PARM -29 340 #define H_ATTR_PARM -30 341 #define H_PORT_PARM -31 342 #define H_MCG_PARM -32 343 #define H_VL_PARM -33 344 #define H_TSIZE_PARM -34 345 #define H_TRACE_PARM -35 346 347 #define H_MASK_PARM -37 348 #define H_MCG_FULL -38 349 #define H_ALIAS_EXIST -39 350 #define H_P_COUNTER -40 351 #define H_TABLE_FULL -41 352 #define H_ALT_TABLE -42 353 #define H_MR_CONDITION -43 354 #define H_NOT_ENOUGH_RESOURCES -44 355 #define H_R_STATE -45 356 #define H_RESCINDEND -46 357 #define H_P2 -55 358 #define H_P3 -56 359 #define H_P4 -57 360 #define H_P5 -58 361 #define H_P6 -59 362 #define H_P7 -60 363 #define H_P8 -61 364 #define H_P9 -62 365 #define H_NOOP -63 366 #define H_UNSUPPORTED -67 367 #define H_OVERLAP -68 368 #define H_UNSUPPORTED_FLAG -256 369 #define H_MULTI_THREADS_ACTIVE -9005 370 371 372 /* Long Busy is a condition that can be returned by the firmware 373 * when a call cannot be completed now, but the identical call 374 * should be retried later. This prevents calls blocking in the 375 * firmware for long periods of time. Annoyingly the firmware can return 376 * a range of return codes, hinting at how long we should wait before 377 * retrying. If you don't care for the hint, the macro below is a good 378 * way to check for the long_busy return codes 379 */ 380 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 381 && (x <= H_LONG_BUSY_END_RANGE)) 382 383 /* Flags */ 384 #define H_LARGE_PAGE (1ULL<<(63-16)) 385 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 386 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 387 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 388 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 389 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 390 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 391 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 392 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 393 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 394 #define H_ANDCOND (1ULL<<(63-33)) 395 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 396 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 397 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 398 #define H_COPY_PAGE (1ULL<<(63-49)) 399 #define H_N (1ULL<<(63-61)) 400 #define H_PP1 (1ULL<<(63-62)) 401 #define H_PP2 (1ULL<<(63-63)) 402 403 /* Values for 2nd argument to H_SET_MODE */ 404 #define H_SET_MODE_RESOURCE_SET_CIABR 1 405 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 406 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 407 #define H_SET_MODE_RESOURCE_LE 4 408 409 /* Flags for H_SET_MODE_RESOURCE_LE */ 410 #define H_SET_MODE_ENDIAN_BIG 0 411 #define H_SET_MODE_ENDIAN_LITTLE 1 412 413 /* VASI States */ 414 #define H_VASI_INVALID 0 415 #define H_VASI_ENABLED 1 416 #define H_VASI_ABORTED 2 417 #define H_VASI_SUSPENDING 3 418 #define H_VASI_SUSPENDED 4 419 #define H_VASI_RESUMED 5 420 #define H_VASI_COMPLETED 6 421 422 /* DABRX flags */ 423 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 424 #define H_DABRX_KERNEL (1ULL<<(63-62)) 425 #define H_DABRX_USER (1ULL<<(63-63)) 426 427 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 428 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 429 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 430 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 431 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 432 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 433 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 434 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 435 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 436 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 437 438 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 439 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 440 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 441 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 442 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 443 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 444 445 /* Each control block has to be on a 4K boundary */ 446 #define H_CB_ALIGNMENT 4096 447 448 /* pSeries hypervisor opcodes */ 449 #define H_REMOVE 0x04 450 #define H_ENTER 0x08 451 #define H_READ 0x0c 452 #define H_CLEAR_MOD 0x10 453 #define H_CLEAR_REF 0x14 454 #define H_PROTECT 0x18 455 #define H_GET_TCE 0x1c 456 #define H_PUT_TCE 0x20 457 #define H_SET_SPRG0 0x24 458 #define H_SET_DABR 0x28 459 #define H_PAGE_INIT 0x2c 460 #define H_SET_ASR 0x30 461 #define H_ASR_ON 0x34 462 #define H_ASR_OFF 0x38 463 #define H_LOGICAL_CI_LOAD 0x3c 464 #define H_LOGICAL_CI_STORE 0x40 465 #define H_LOGICAL_CACHE_LOAD 0x44 466 #define H_LOGICAL_CACHE_STORE 0x48 467 #define H_LOGICAL_ICBI 0x4c 468 #define H_LOGICAL_DCBF 0x50 469 #define H_GET_TERM_CHAR 0x54 470 #define H_PUT_TERM_CHAR 0x58 471 #define H_REAL_TO_LOGICAL 0x5c 472 #define H_HYPERVISOR_DATA 0x60 473 #define H_EOI 0x64 474 #define H_CPPR 0x68 475 #define H_IPI 0x6c 476 #define H_IPOLL 0x70 477 #define H_XIRR 0x74 478 #define H_PERFMON 0x7c 479 #define H_MIGRATE_DMA 0x78 480 #define H_REGISTER_VPA 0xDC 481 #define H_CEDE 0xE0 482 #define H_CONFER 0xE4 483 #define H_PROD 0xE8 484 #define H_GET_PPP 0xEC 485 #define H_SET_PPP 0xF0 486 #define H_PURR 0xF4 487 #define H_PIC 0xF8 488 #define H_REG_CRQ 0xFC 489 #define H_FREE_CRQ 0x100 490 #define H_VIO_SIGNAL 0x104 491 #define H_SEND_CRQ 0x108 492 #define H_COPY_RDMA 0x110 493 #define H_REGISTER_LOGICAL_LAN 0x114 494 #define H_FREE_LOGICAL_LAN 0x118 495 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 496 #define H_SEND_LOGICAL_LAN 0x120 497 #define H_BULK_REMOVE 0x124 498 #define H_MULTICAST_CTRL 0x130 499 #define H_SET_XDABR 0x134 500 #define H_STUFF_TCE 0x138 501 #define H_PUT_TCE_INDIRECT 0x13C 502 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 503 #define H_VTERM_PARTNER_INFO 0x150 504 #define H_REGISTER_VTERM 0x154 505 #define H_FREE_VTERM 0x158 506 #define H_RESET_EVENTS 0x15C 507 #define H_ALLOC_RESOURCE 0x160 508 #define H_FREE_RESOURCE 0x164 509 #define H_MODIFY_QP 0x168 510 #define H_QUERY_QP 0x16C 511 #define H_REREGISTER_PMR 0x170 512 #define H_REGISTER_SMR 0x174 513 #define H_QUERY_MR 0x178 514 #define H_QUERY_MW 0x17C 515 #define H_QUERY_HCA 0x180 516 #define H_QUERY_PORT 0x184 517 #define H_MODIFY_PORT 0x188 518 #define H_DEFINE_AQP1 0x18C 519 #define H_GET_TRACE_BUFFER 0x190 520 #define H_DEFINE_AQP0 0x194 521 #define H_RESIZE_MR 0x198 522 #define H_ATTACH_MCQP 0x19C 523 #define H_DETACH_MCQP 0x1A0 524 #define H_CREATE_RPT 0x1A4 525 #define H_REMOVE_RPT 0x1A8 526 #define H_REGISTER_RPAGES 0x1AC 527 #define H_DISABLE_AND_GETC 0x1B0 528 #define H_ERROR_DATA 0x1B4 529 #define H_GET_HCA_INFO 0x1B8 530 #define H_GET_PERF_COUNT 0x1BC 531 #define H_MANAGE_TRACE 0x1C0 532 #define H_GET_CPU_CHARACTERISTICS 0x1C8 533 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 534 #define H_QUERY_INT_STATE 0x1E4 535 #define H_POLL_PENDING 0x1D8 536 #define H_ILLAN_ATTRIBUTES 0x244 537 #define H_MODIFY_HEA_QP 0x250 538 #define H_QUERY_HEA_QP 0x254 539 #define H_QUERY_HEA 0x258 540 #define H_QUERY_HEA_PORT 0x25C 541 #define H_MODIFY_HEA_PORT 0x260 542 #define H_REG_BCMC 0x264 543 #define H_DEREG_BCMC 0x268 544 #define H_REGISTER_HEA_RPAGES 0x26C 545 #define H_DISABLE_AND_GET_HEA 0x270 546 #define H_GET_HEA_INFO 0x274 547 #define H_ALLOC_HEA_RESOURCE 0x278 548 #define H_ADD_CONN 0x284 549 #define H_DEL_CONN 0x288 550 #define H_JOIN 0x298 551 #define H_VASI_STATE 0x2A4 552 #define H_ENABLE_CRQ 0x2B0 553 #define H_GET_EM_PARMS 0x2B8 554 #define H_SET_MPP 0x2D0 555 #define H_GET_MPP 0x2D4 556 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 557 #define H_XIRR_X 0x2FC 558 #define H_RANDOM 0x300 559 #define H_SET_MODE 0x31C 560 #define H_RESIZE_HPT_PREPARE 0x36C 561 #define H_RESIZE_HPT_COMMIT 0x370 562 #define H_CLEAN_SLB 0x374 563 #define H_INVALIDATE_PID 0x378 564 #define H_REGISTER_PROC_TBL 0x37C 565 #define H_SIGNAL_SYS_RESET 0x380 566 567 #define H_INT_GET_SOURCE_INFO 0x3A8 568 #define H_INT_SET_SOURCE_CONFIG 0x3AC 569 #define H_INT_GET_SOURCE_CONFIG 0x3B0 570 #define H_INT_GET_QUEUE_INFO 0x3B4 571 #define H_INT_SET_QUEUE_CONFIG 0x3B8 572 #define H_INT_GET_QUEUE_CONFIG 0x3BC 573 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 574 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 575 #define H_INT_ESB 0x3C8 576 #define H_INT_SYNC 0x3CC 577 #define H_INT_RESET 0x3D0 578 #define H_SCM_READ_METADATA 0x3E4 579 #define H_SCM_WRITE_METADATA 0x3E8 580 #define H_SCM_BIND_MEM 0x3EC 581 #define H_SCM_UNBIND_MEM 0x3F0 582 #define H_SCM_UNBIND_ALL 0x3FC 583 #define H_SCM_HEALTH 0x400 584 #define H_RPT_INVALIDATE 0x448 585 #define H_SCM_FLUSH 0x44C 586 #define H_WATCHDOG 0x45C 587 588 #define MAX_HCALL_OPCODE H_WATCHDOG 589 590 /* The hcalls above are standardized in PAPR and implemented by pHyp 591 * as well. 592 * 593 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 594 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 595 * for "platform-specific" hcalls. 596 */ 597 #define KVMPPC_HCALL_BASE 0xf000 598 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 599 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 600 /* Client Architecture support */ 601 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 602 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 603 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 604 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 605 606 /* Platform-specific hcalls used for nested HV KVM */ 607 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 608 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 609 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 610 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 611 612 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 613 614 /* 615 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 616 * Secure VM mode via an Ultravisor / Protected Execution Facility 617 */ 618 #define SVM_HCALL_BASE 0xEF00 619 #define SVM_H_TPM_COMM 0xEF10 620 #define SVM_HCALL_MAX SVM_H_TPM_COMM 621 622 /* 623 * Register state for entering a nested guest with H_ENTER_NESTED. 624 * New member must be added at the end. 625 */ 626 struct kvmppc_hv_guest_state { 627 uint64_t version; /* version of this structure layout, must be first */ 628 uint32_t lpid; 629 uint32_t vcpu_token; 630 /* These registers are hypervisor privileged (at least for writing) */ 631 uint64_t lpcr; 632 uint64_t pcr; 633 uint64_t amor; 634 uint64_t dpdes; 635 uint64_t hfscr; 636 int64_t tb_offset; 637 uint64_t dawr0; 638 uint64_t dawrx0; 639 uint64_t ciabr; 640 uint64_t hdec_expiry; 641 uint64_t purr; 642 uint64_t spurr; 643 uint64_t ic; 644 uint64_t vtb; 645 uint64_t hdar; 646 uint64_t hdsisr; 647 uint64_t heir; 648 uint64_t asdr; 649 /* These are OS privileged but need to be set late in guest entry */ 650 uint64_t srr0; 651 uint64_t srr1; 652 uint64_t sprg[4]; 653 uint64_t pidr; 654 uint64_t cfar; 655 uint64_t ppr; 656 /* Version 1 ends here */ 657 uint64_t dawr1; 658 uint64_t dawrx1; 659 /* Version 2 ends here */ 660 }; 661 662 /* Latest version of hv_guest_state structure */ 663 #define HV_GUEST_STATE_VERSION 2 664 665 /* Linux 64-bit powerpc pt_regs struct, used by nested HV */ 666 struct kvmppc_pt_regs { 667 uint64_t gpr[32]; 668 uint64_t nip; 669 uint64_t msr; 670 uint64_t orig_gpr3; /* Used for restarting system calls */ 671 uint64_t ctr; 672 uint64_t link; 673 uint64_t xer; 674 uint64_t ccr; 675 uint64_t softe; /* Soft enabled/disabled */ 676 uint64_t trap; /* Reason for being here */ 677 uint64_t dar; /* Fault registers */ 678 uint64_t dsisr; /* on 4xx/Book-E used for ESR */ 679 uint64_t result; /* Result of a system call */ 680 }; 681 682 typedef struct SpaprDeviceTreeUpdateHeader { 683 uint32_t version_id; 684 } SpaprDeviceTreeUpdateHeader; 685 686 #define hcall_dprintf(fmt, ...) \ 687 do { \ 688 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 689 } while (0) 690 691 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 692 target_ulong opcode, 693 target_ulong *args); 694 695 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 696 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 697 target_ulong *args); 698 699 void spapr_exit_nested(PowerPCCPU *cpu, int excp); 700 701 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 702 target_ulong shift); 703 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 704 target_ulong flags, target_ulong shift); 705 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 706 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 707 708 /* Virtual Processor Area structure constants */ 709 #define VPA_MIN_SIZE 640 710 #define VPA_SIZE_OFFSET 0x4 711 #define VPA_SHARED_PROC_OFFSET 0x9 712 #define VPA_SHARED_PROC_VAL 0x2 713 #define VPA_DISPATCH_COUNTER 0x100 714 715 /* ibm,set-eeh-option */ 716 #define RTAS_EEH_DISABLE 0 717 #define RTAS_EEH_ENABLE 1 718 #define RTAS_EEH_THAW_IO 2 719 #define RTAS_EEH_THAW_DMA 3 720 721 /* ibm,get-config-addr-info2 */ 722 #define RTAS_GET_PE_ADDR 0 723 #define RTAS_GET_PE_MODE 1 724 #define RTAS_PE_MODE_NONE 0 725 #define RTAS_PE_MODE_NOT_SHARED 1 726 #define RTAS_PE_MODE_SHARED 2 727 728 /* ibm,read-slot-reset-state2 */ 729 #define RTAS_EEH_PE_STATE_NORMAL 0 730 #define RTAS_EEH_PE_STATE_RESET 1 731 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 732 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 733 #define RTAS_EEH_PE_STATE_UNAVAIL 5 734 #define RTAS_EEH_NOT_SUPPORT 0 735 #define RTAS_EEH_SUPPORT 1 736 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 737 #define RTAS_EEH_PE_RECOVER_INFO 0 738 739 /* ibm,set-slot-reset */ 740 #define RTAS_SLOT_RESET_DEACTIVATE 0 741 #define RTAS_SLOT_RESET_HOT 1 742 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 743 744 /* ibm,slot-error-detail */ 745 #define RTAS_SLOT_TEMP_ERR_LOG 1 746 #define RTAS_SLOT_PERM_ERR_LOG 2 747 748 /* RTAS return codes */ 749 #define RTAS_OUT_SUCCESS 0 750 #define RTAS_OUT_NO_ERRORS_FOUND 1 751 #define RTAS_OUT_HW_ERROR -1 752 #define RTAS_OUT_BUSY -2 753 #define RTAS_OUT_PARAM_ERROR -3 754 #define RTAS_OUT_NOT_SUPPORTED -3 755 #define RTAS_OUT_NO_SUCH_INDICATOR -3 756 #define RTAS_OUT_NOT_AUTHORIZED -9002 757 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 758 759 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 760 #define RTAS_DDW_PGSIZE_4K 0x01 761 #define RTAS_DDW_PGSIZE_64K 0x02 762 #define RTAS_DDW_PGSIZE_16M 0x04 763 #define RTAS_DDW_PGSIZE_32M 0x08 764 #define RTAS_DDW_PGSIZE_64M 0x10 765 #define RTAS_DDW_PGSIZE_128M 0x20 766 #define RTAS_DDW_PGSIZE_256M 0x40 767 #define RTAS_DDW_PGSIZE_16G 0x80 768 #define RTAS_DDW_PGSIZE_2M 0x100 769 770 /* RTAS tokens */ 771 #define RTAS_TOKEN_BASE 0x2000 772 773 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 774 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 775 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 776 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 777 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 778 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 779 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 780 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 781 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 782 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 783 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 784 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 785 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 786 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 787 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 788 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 789 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 790 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 791 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 792 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 793 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 794 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 795 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 796 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 797 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 798 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 799 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 800 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 801 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 802 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 803 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 804 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 805 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 806 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 807 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 808 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 809 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 810 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 811 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 812 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 813 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 814 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 815 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 816 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 817 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 818 819 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 820 821 /* RTAS ibm,get-system-parameter token values */ 822 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 823 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 824 #define RTAS_SYSPARM_UUID 48 825 826 /* RTAS indicator/sensor types 827 * 828 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 829 * 830 * NOTE: currently only DR-related sensors are implemented here 831 */ 832 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 833 #define RTAS_SENSOR_TYPE_DR 9002 834 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 835 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 836 837 /* Possible values for the platform-processor-diagnostics-run-mode parameter 838 * of the RTAS ibm,get-system-parameter call. 839 */ 840 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 841 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 842 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 843 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 844 845 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 846 { 847 return addr & ~0xF000000000000000ULL; 848 } 849 850 static inline uint32_t rtas_ld(target_ulong phys, int n) 851 { 852 return ldl_be_phys(&address_space_memory, 853 ppc64_phys_to_real(phys + 4 * n)); 854 } 855 856 static inline uint64_t rtas_ldq(target_ulong phys, int n) 857 { 858 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 859 } 860 861 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 862 { 863 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 864 } 865 866 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 867 uint32_t token, 868 uint32_t nargs, target_ulong args, 869 uint32_t nret, target_ulong rets); 870 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 871 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 872 uint32_t token, uint32_t nargs, target_ulong args, 873 uint32_t nret, target_ulong rets); 874 void spapr_dt_rtas_tokens(void *fdt, int rtas); 875 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 876 877 #define SPAPR_TCE_PAGE_SHIFT 12 878 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 879 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 880 881 #define SPAPR_VIO_BASE_LIOBN 0x00000000 882 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 883 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 884 (0x80000000 | ((phb_index) << 8) | (window_num)) 885 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 886 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 887 888 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 889 #define RTAS_ERROR_LOG_MAX 2048 890 891 /* Offset from rtas-base where error log is placed */ 892 #define RTAS_ERROR_LOG_OFFSET 0x30 893 894 #define RTAS_EVENT_SCAN_RATE 1 895 896 /* This helper should be used to encode interrupt specifiers when the related 897 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 898 * VIO devices, RTAS event sources and PHBs). 899 */ 900 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 901 { 902 intspec[0] = cpu_to_be32(irq); 903 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 904 } 905 906 907 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 908 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 909 910 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 911 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 912 TYPE_SPAPR_IOMMU_MEMORY_REGION) 913 914 struct SpaprTceTable { 915 DeviceState parent; 916 uint32_t liobn; 917 uint32_t nb_table; 918 uint64_t bus_offset; 919 uint32_t page_shift; 920 uint64_t *table; 921 uint32_t mig_nb_table; 922 uint64_t *mig_table; 923 bool bypass; 924 bool need_vfio; 925 bool skipping_replay; 926 bool def_win; 927 int fd; 928 MemoryRegion root; 929 IOMMUMemoryRegion iommu; 930 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 931 QLIST_ENTRY(SpaprTceTable) list; 932 }; 933 934 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 935 936 struct SpaprEventLogEntry { 937 uint32_t summary; 938 uint32_t extended_length; 939 void *extended_log; 940 QTAILQ_ENTRY(SpaprEventLogEntry) next; 941 }; 942 943 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 944 void spapr_events_init(SpaprMachineState *sm); 945 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 946 void close_htab_fd(SpaprMachineState *spapr); 947 void spapr_setup_hpt(SpaprMachineState *spapr); 948 void spapr_free_hpt(SpaprMachineState *spapr); 949 void spapr_check_mmu_mode(bool guest_radix); 950 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 951 void spapr_tce_table_enable(SpaprTceTable *tcet, 952 uint32_t page_shift, uint64_t bus_offset, 953 uint32_t nb_table); 954 void spapr_tce_table_disable(SpaprTceTable *tcet); 955 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 956 957 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 958 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 959 uint32_t liobn, uint64_t window, uint32_t size); 960 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 961 SpaprTceTable *tcet); 962 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 963 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 964 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 965 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 966 uint32_t count); 967 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 968 uint32_t count); 969 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 970 uint32_t count, uint32_t index); 971 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 972 uint32_t count, uint32_t index); 973 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 974 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 975 void spapr_clear_pending_events(SpaprMachineState *spapr); 976 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 977 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 978 int spapr_max_server_number(SpaprMachineState *spapr); 979 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 980 uint64_t pte0, uint64_t pte1); 981 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 982 983 /* DRC callbacks. */ 984 void spapr_core_release(DeviceState *dev); 985 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 986 void *fdt, int *fdt_start_offset, Error **errp); 987 void spapr_lmb_release(DeviceState *dev); 988 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 989 void *fdt, int *fdt_start_offset, Error **errp); 990 void spapr_phb_release(DeviceState *dev); 991 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 992 void *fdt, int *fdt_start_offset, Error **errp); 993 994 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 995 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 996 997 #define TYPE_SPAPR_RNG "spapr-rng" 998 999 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 1000 1001 /* 1002 * This defines the maximum number of DIMM slots we can have for sPAPR 1003 * guest. This is not defined by sPAPR but we are defining it to 32 slots 1004 * based on default number of slots provided by PowerPC kernel. 1005 */ 1006 #define SPAPR_MAX_RAM_SLOTS 32 1007 1008 /* 1GB alignment for hotplug memory region */ 1009 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 1010 1011 /* 1012 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 1013 * property under ibm,dynamic-reconfiguration-memory node. 1014 */ 1015 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 1016 1017 /* 1018 * Defines for flag value in ibm,dynamic-memory property under 1019 * ibm,dynamic-reconfiguration-memory node. 1020 */ 1021 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 1022 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 1023 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 1024 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 1025 1026 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 1027 1028 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 1029 1030 int spapr_get_vcpu_id(PowerPCCPU *cpu); 1031 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 1032 PowerPCCPU *spapr_find_cpu(int vcpu_id); 1033 1034 int spapr_caps_pre_load(void *opaque); 1035 int spapr_caps_pre_save(void *opaque); 1036 1037 /* 1038 * Handling of optional capabilities 1039 */ 1040 extern const VMStateDescription vmstate_spapr_cap_htm; 1041 extern const VMStateDescription vmstate_spapr_cap_vsx; 1042 extern const VMStateDescription vmstate_spapr_cap_dfp; 1043 extern const VMStateDescription vmstate_spapr_cap_cfpc; 1044 extern const VMStateDescription vmstate_spapr_cap_sbbc; 1045 extern const VMStateDescription vmstate_spapr_cap_ibs; 1046 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 1047 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 1048 extern const VMStateDescription vmstate_spapr_cap_large_decr; 1049 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 1050 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 1051 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 1052 extern const VMStateDescription vmstate_spapr_wdt; 1053 1054 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 1055 { 1056 return spapr->eff.caps[cap]; 1057 } 1058 1059 void spapr_caps_init(SpaprMachineState *spapr); 1060 void spapr_caps_apply(SpaprMachineState *spapr); 1061 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 1062 void spapr_caps_add_properties(SpaprMachineClass *smc); 1063 int spapr_caps_post_migration(SpaprMachineState *spapr); 1064 1065 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1066 Error **errp); 1067 /* 1068 * XIVE definitions 1069 */ 1070 #define SPAPR_OV5_XIVE_LEGACY 0x0 1071 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1072 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1073 1074 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1075 hwaddr spapr_get_rtas_addr(void); 1076 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1077 1078 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1079 void spapr_vof_quiesce(MachineState *ms); 1080 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1081 void *val, int vallen); 1082 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1083 target_ulong opcode, target_ulong *args); 1084 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1085 CPUState *cs, 1086 target_ulong ovec_addr); 1087 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1088 1089 /* H_WATCHDOG */ 1090 void spapr_watchdog_init(SpaprMachineState *spapr); 1091 1092 #endif /* HW_SPAPR_H */ 1093