1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 10 struct VIOsPAPRBus; 11 struct sPAPRPHBState; 12 struct sPAPRNVRAM; 13 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 16 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 17 #define SPAPR_ENTRY_POINT 0x100 18 19 typedef struct sPAPRMachineClass sPAPRMachineClass; 20 typedef struct sPAPRMachineState sPAPRMachineState; 21 22 #define TYPE_SPAPR_MACHINE "spapr-machine" 23 #define SPAPR_MACHINE(obj) \ 24 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 25 #define SPAPR_MACHINE_GET_CLASS(obj) \ 26 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 27 #define SPAPR_MACHINE_CLASS(klass) \ 28 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 29 30 /** 31 * sPAPRMachineClass: 32 */ 33 struct sPAPRMachineClass { 34 /*< private >*/ 35 MachineClass parent_class; 36 37 /*< public >*/ 38 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 39 }; 40 41 /** 42 * sPAPRMachineState: 43 */ 44 struct sPAPRMachineState { 45 /*< private >*/ 46 MachineState parent_obj; 47 48 struct VIOsPAPRBus *vio_bus; 49 QLIST_HEAD(, sPAPRPHBState) phbs; 50 struct sPAPRNVRAM *nvram; 51 XICSState *icp; 52 DeviceState *rtc; 53 54 void *htab; 55 uint32_t htab_shift; 56 hwaddr rma_size; 57 int vrma_adjust; 58 hwaddr fdt_addr, rtas_addr; 59 ssize_t rtas_size; 60 void *rtas_blob; 61 void *fdt_skel; 62 uint64_t rtc_offset; /* Now used only during incoming migration */ 63 struct PPCTimebase tb; 64 bool has_graphics; 65 66 uint32_t check_exception_irq; 67 Notifier epow_notifier; 68 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 69 70 /* Migration state */ 71 int htab_save_index; 72 bool htab_first_pass; 73 int htab_fd; 74 bool htab_fd_stale; 75 76 /* RTAS state */ 77 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 78 79 /*< public >*/ 80 char *kvm_type; 81 MemoryHotplugState hotplug_memory; 82 }; 83 84 #define H_SUCCESS 0 85 #define H_BUSY 1 /* Hardware busy -- retry later */ 86 #define H_CLOSED 2 /* Resource closed */ 87 #define H_NOT_AVAILABLE 3 88 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 89 #define H_PARTIAL 5 90 #define H_IN_PROGRESS 14 /* Kind of like busy */ 91 #define H_PAGE_REGISTERED 15 92 #define H_PARTIAL_STORE 16 93 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 94 #define H_CONTINUE 18 /* Returned from H_Join on success */ 95 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 96 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 97 is a good time to retry */ 98 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 99 is a good time to retry */ 100 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 101 is a good time to retry */ 102 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 103 is a good time to retry */ 104 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 105 is a good time to retry */ 106 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 107 is a good time to retry */ 108 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 109 #define H_HARDWARE -1 /* Hardware error */ 110 #define H_FUNCTION -2 /* Function not supported */ 111 #define H_PRIVILEGE -3 /* Caller not privileged */ 112 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 113 #define H_BAD_MODE -5 /* Illegal msr value */ 114 #define H_PTEG_FULL -6 /* PTEG is full */ 115 #define H_NOT_FOUND -7 /* PTE was not found" */ 116 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 117 #define H_NO_MEM -9 118 #define H_AUTHORITY -10 119 #define H_PERMISSION -11 120 #define H_DROPPED -12 121 #define H_SOURCE_PARM -13 122 #define H_DEST_PARM -14 123 #define H_REMOTE_PARM -15 124 #define H_RESOURCE -16 125 #define H_ADAPTER_PARM -17 126 #define H_RH_PARM -18 127 #define H_RCQ_PARM -19 128 #define H_SCQ_PARM -20 129 #define H_EQ_PARM -21 130 #define H_RT_PARM -22 131 #define H_ST_PARM -23 132 #define H_SIGT_PARM -24 133 #define H_TOKEN_PARM -25 134 #define H_MLENGTH_PARM -27 135 #define H_MEM_PARM -28 136 #define H_MEM_ACCESS_PARM -29 137 #define H_ATTR_PARM -30 138 #define H_PORT_PARM -31 139 #define H_MCG_PARM -32 140 #define H_VL_PARM -33 141 #define H_TSIZE_PARM -34 142 #define H_TRACE_PARM -35 143 144 #define H_MASK_PARM -37 145 #define H_MCG_FULL -38 146 #define H_ALIAS_EXIST -39 147 #define H_P_COUNTER -40 148 #define H_TABLE_FULL -41 149 #define H_ALT_TABLE -42 150 #define H_MR_CONDITION -43 151 #define H_NOT_ENOUGH_RESOURCES -44 152 #define H_R_STATE -45 153 #define H_RESCINDEND -46 154 #define H_P2 -55 155 #define H_P3 -56 156 #define H_P4 -57 157 #define H_P5 -58 158 #define H_P6 -59 159 #define H_P7 -60 160 #define H_P8 -61 161 #define H_P9 -62 162 #define H_UNSUPPORTED_FLAG -256 163 #define H_MULTI_THREADS_ACTIVE -9005 164 165 166 /* Long Busy is a condition that can be returned by the firmware 167 * when a call cannot be completed now, but the identical call 168 * should be retried later. This prevents calls blocking in the 169 * firmware for long periods of time. Annoyingly the firmware can return 170 * a range of return codes, hinting at how long we should wait before 171 * retrying. If you don't care for the hint, the macro below is a good 172 * way to check for the long_busy return codes 173 */ 174 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 175 && (x <= H_LONG_BUSY_END_RANGE)) 176 177 /* Flags */ 178 #define H_LARGE_PAGE (1ULL<<(63-16)) 179 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 180 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 181 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 182 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 183 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 184 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 185 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 186 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 187 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 188 #define H_ANDCOND (1ULL<<(63-33)) 189 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 190 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 191 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 192 #define H_COPY_PAGE (1ULL<<(63-49)) 193 #define H_N (1ULL<<(63-61)) 194 #define H_PP1 (1ULL<<(63-62)) 195 #define H_PP2 (1ULL<<(63-63)) 196 197 /* Values for 2nd argument to H_SET_MODE */ 198 #define H_SET_MODE_RESOURCE_SET_CIABR 1 199 #define H_SET_MODE_RESOURCE_SET_DAWR 2 200 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 201 #define H_SET_MODE_RESOURCE_LE 4 202 203 /* Flags for H_SET_MODE_RESOURCE_LE */ 204 #define H_SET_MODE_ENDIAN_BIG 0 205 #define H_SET_MODE_ENDIAN_LITTLE 1 206 207 /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 208 #define H_SET_MODE_ADDR_TRANS_NONE 0 209 #define H_SET_MODE_ADDR_TRANS_0001_8000 2 210 #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 211 212 /* VASI States */ 213 #define H_VASI_INVALID 0 214 #define H_VASI_ENABLED 1 215 #define H_VASI_ABORTED 2 216 #define H_VASI_SUSPENDING 3 217 #define H_VASI_SUSPENDED 4 218 #define H_VASI_RESUMED 5 219 #define H_VASI_COMPLETED 6 220 221 /* DABRX flags */ 222 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 223 #define H_DABRX_KERNEL (1ULL<<(63-62)) 224 #define H_DABRX_USER (1ULL<<(63-63)) 225 226 /* Each control block has to be on a 4K boundary */ 227 #define H_CB_ALIGNMENT 4096 228 229 /* pSeries hypervisor opcodes */ 230 #define H_REMOVE 0x04 231 #define H_ENTER 0x08 232 #define H_READ 0x0c 233 #define H_CLEAR_MOD 0x10 234 #define H_CLEAR_REF 0x14 235 #define H_PROTECT 0x18 236 #define H_GET_TCE 0x1c 237 #define H_PUT_TCE 0x20 238 #define H_SET_SPRG0 0x24 239 #define H_SET_DABR 0x28 240 #define H_PAGE_INIT 0x2c 241 #define H_SET_ASR 0x30 242 #define H_ASR_ON 0x34 243 #define H_ASR_OFF 0x38 244 #define H_LOGICAL_CI_LOAD 0x3c 245 #define H_LOGICAL_CI_STORE 0x40 246 #define H_LOGICAL_CACHE_LOAD 0x44 247 #define H_LOGICAL_CACHE_STORE 0x48 248 #define H_LOGICAL_ICBI 0x4c 249 #define H_LOGICAL_DCBF 0x50 250 #define H_GET_TERM_CHAR 0x54 251 #define H_PUT_TERM_CHAR 0x58 252 #define H_REAL_TO_LOGICAL 0x5c 253 #define H_HYPERVISOR_DATA 0x60 254 #define H_EOI 0x64 255 #define H_CPPR 0x68 256 #define H_IPI 0x6c 257 #define H_IPOLL 0x70 258 #define H_XIRR 0x74 259 #define H_PERFMON 0x7c 260 #define H_MIGRATE_DMA 0x78 261 #define H_REGISTER_VPA 0xDC 262 #define H_CEDE 0xE0 263 #define H_CONFER 0xE4 264 #define H_PROD 0xE8 265 #define H_GET_PPP 0xEC 266 #define H_SET_PPP 0xF0 267 #define H_PURR 0xF4 268 #define H_PIC 0xF8 269 #define H_REG_CRQ 0xFC 270 #define H_FREE_CRQ 0x100 271 #define H_VIO_SIGNAL 0x104 272 #define H_SEND_CRQ 0x108 273 #define H_COPY_RDMA 0x110 274 #define H_REGISTER_LOGICAL_LAN 0x114 275 #define H_FREE_LOGICAL_LAN 0x118 276 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 277 #define H_SEND_LOGICAL_LAN 0x120 278 #define H_BULK_REMOVE 0x124 279 #define H_MULTICAST_CTRL 0x130 280 #define H_SET_XDABR 0x134 281 #define H_STUFF_TCE 0x138 282 #define H_PUT_TCE_INDIRECT 0x13C 283 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 284 #define H_VTERM_PARTNER_INFO 0x150 285 #define H_REGISTER_VTERM 0x154 286 #define H_FREE_VTERM 0x158 287 #define H_RESET_EVENTS 0x15C 288 #define H_ALLOC_RESOURCE 0x160 289 #define H_FREE_RESOURCE 0x164 290 #define H_MODIFY_QP 0x168 291 #define H_QUERY_QP 0x16C 292 #define H_REREGISTER_PMR 0x170 293 #define H_REGISTER_SMR 0x174 294 #define H_QUERY_MR 0x178 295 #define H_QUERY_MW 0x17C 296 #define H_QUERY_HCA 0x180 297 #define H_QUERY_PORT 0x184 298 #define H_MODIFY_PORT 0x188 299 #define H_DEFINE_AQP1 0x18C 300 #define H_GET_TRACE_BUFFER 0x190 301 #define H_DEFINE_AQP0 0x194 302 #define H_RESIZE_MR 0x198 303 #define H_ATTACH_MCQP 0x19C 304 #define H_DETACH_MCQP 0x1A0 305 #define H_CREATE_RPT 0x1A4 306 #define H_REMOVE_RPT 0x1A8 307 #define H_REGISTER_RPAGES 0x1AC 308 #define H_DISABLE_AND_GETC 0x1B0 309 #define H_ERROR_DATA 0x1B4 310 #define H_GET_HCA_INFO 0x1B8 311 #define H_GET_PERF_COUNT 0x1BC 312 #define H_MANAGE_TRACE 0x1C0 313 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 314 #define H_QUERY_INT_STATE 0x1E4 315 #define H_POLL_PENDING 0x1D8 316 #define H_ILLAN_ATTRIBUTES 0x244 317 #define H_MODIFY_HEA_QP 0x250 318 #define H_QUERY_HEA_QP 0x254 319 #define H_QUERY_HEA 0x258 320 #define H_QUERY_HEA_PORT 0x25C 321 #define H_MODIFY_HEA_PORT 0x260 322 #define H_REG_BCMC 0x264 323 #define H_DEREG_BCMC 0x268 324 #define H_REGISTER_HEA_RPAGES 0x26C 325 #define H_DISABLE_AND_GET_HEA 0x270 326 #define H_GET_HEA_INFO 0x274 327 #define H_ALLOC_HEA_RESOURCE 0x278 328 #define H_ADD_CONN 0x284 329 #define H_DEL_CONN 0x288 330 #define H_JOIN 0x298 331 #define H_VASI_STATE 0x2A4 332 #define H_ENABLE_CRQ 0x2B0 333 #define H_GET_EM_PARMS 0x2B8 334 #define H_SET_MPP 0x2D0 335 #define H_GET_MPP 0x2D4 336 #define H_XIRR_X 0x2FC 337 #define H_SET_MODE 0x31C 338 #define MAX_HCALL_OPCODE H_SET_MODE 339 340 /* The hcalls above are standardized in PAPR and implemented by pHyp 341 * as well. 342 * 343 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 344 * So far we just need one for H_RTAS, but in future we'll need more 345 * for extensions like virtio. We put those into the 0xf000-0xfffc 346 * range which is reserved by PAPR for "platform-specific" hcalls. 347 */ 348 #define KVMPPC_HCALL_BASE 0xf000 349 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 350 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 351 /* Client Architecture support */ 352 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 353 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 354 355 typedef struct sPAPRDeviceTreeUpdateHeader { 356 uint32_t version_id; 357 } sPAPRDeviceTreeUpdateHeader; 358 359 #define hcall_dprintf(fmt, ...) \ 360 do { \ 361 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 362 } while (0) 363 364 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 365 target_ulong opcode, 366 target_ulong *args); 367 368 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 369 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 370 target_ulong *args); 371 372 int spapr_allocate_irq(int hint, bool lsi); 373 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 374 375 /* ibm,set-eeh-option */ 376 #define RTAS_EEH_DISABLE 0 377 #define RTAS_EEH_ENABLE 1 378 #define RTAS_EEH_THAW_IO 2 379 #define RTAS_EEH_THAW_DMA 3 380 381 /* ibm,get-config-addr-info2 */ 382 #define RTAS_GET_PE_ADDR 0 383 #define RTAS_GET_PE_MODE 1 384 #define RTAS_PE_MODE_NONE 0 385 #define RTAS_PE_MODE_NOT_SHARED 1 386 #define RTAS_PE_MODE_SHARED 2 387 388 /* ibm,read-slot-reset-state2 */ 389 #define RTAS_EEH_PE_STATE_NORMAL 0 390 #define RTAS_EEH_PE_STATE_RESET 1 391 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 392 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 393 #define RTAS_EEH_PE_STATE_UNAVAIL 5 394 #define RTAS_EEH_NOT_SUPPORT 0 395 #define RTAS_EEH_SUPPORT 1 396 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 397 #define RTAS_EEH_PE_RECOVER_INFO 0 398 399 /* ibm,set-slot-reset */ 400 #define RTAS_SLOT_RESET_DEACTIVATE 0 401 #define RTAS_SLOT_RESET_HOT 1 402 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 403 404 /* ibm,slot-error-detail */ 405 #define RTAS_SLOT_TEMP_ERR_LOG 1 406 #define RTAS_SLOT_PERM_ERR_LOG 2 407 408 /* RTAS return codes */ 409 #define RTAS_OUT_SUCCESS 0 410 #define RTAS_OUT_NO_ERRORS_FOUND 1 411 #define RTAS_OUT_HW_ERROR -1 412 #define RTAS_OUT_BUSY -2 413 #define RTAS_OUT_PARAM_ERROR -3 414 #define RTAS_OUT_NOT_SUPPORTED -3 415 #define RTAS_OUT_NO_SUCH_INDICATOR -3 416 #define RTAS_OUT_NOT_AUTHORIZED -9002 417 418 /* RTAS tokens */ 419 #define RTAS_TOKEN_BASE 0x2000 420 421 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 422 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 423 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 424 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 425 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 426 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 427 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 428 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 429 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 430 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 431 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 432 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 433 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 434 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 435 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 436 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 437 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 438 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 439 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 440 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 441 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 442 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 443 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 444 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 445 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 446 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 447 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 448 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 449 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 450 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 451 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 452 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 453 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 454 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 455 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 456 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 457 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 458 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 459 460 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) 461 462 /* RTAS ibm,get-system-parameter token values */ 463 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 464 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 465 #define RTAS_SYSPARM_UUID 48 466 467 /* RTAS indicator/sensor types 468 * 469 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 470 * 471 * NOTE: currently only DR-related sensors are implemented here 472 */ 473 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 474 #define RTAS_SENSOR_TYPE_DR 9002 475 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 476 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 477 478 /* Possible values for the platform-processor-diagnostics-run-mode parameter 479 * of the RTAS ibm,get-system-parameter call. 480 */ 481 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 482 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 483 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 484 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 485 486 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 487 { 488 return addr & ~0xF000000000000000ULL; 489 } 490 491 static inline uint32_t rtas_ld(target_ulong phys, int n) 492 { 493 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 494 } 495 496 static inline uint64_t rtas_ldq(target_ulong phys, int n) 497 { 498 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 499 } 500 501 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 502 { 503 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 504 } 505 506 static inline void rtas_st_buffer_direct(target_ulong phys, 507 target_ulong phys_len, 508 uint8_t *buffer, uint16_t buffer_len) 509 { 510 cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer, 511 MIN(buffer_len, phys_len)); 512 } 513 514 static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, 515 uint8_t *buffer, uint16_t buffer_len) 516 { 517 if (phys_len < 2) { 518 return; 519 } 520 stw_be_phys(&address_space_memory, 521 ppc64_phys_to_real(phys), buffer_len); 522 rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len); 523 } 524 525 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 526 uint32_t token, 527 uint32_t nargs, target_ulong args, 528 uint32_t nret, target_ulong rets); 529 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 530 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 531 uint32_t token, uint32_t nargs, target_ulong args, 532 uint32_t nret, target_ulong rets); 533 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 534 hwaddr rtas_size); 535 536 #define SPAPR_TCE_PAGE_SHIFT 12 537 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 538 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 539 540 #define SPAPR_VIO_BASE_LIOBN 0x00000000 541 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 542 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 543 (0x80000000 | ((phb_index) << 8) | (window_num)) 544 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 545 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 546 547 #define RTAS_ERROR_LOG_MAX 2048 548 549 #define RTAS_EVENT_SCAN_RATE 1 550 551 typedef struct sPAPRTCETable sPAPRTCETable; 552 553 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 554 #define SPAPR_TCE_TABLE(obj) \ 555 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 556 557 struct sPAPRTCETable { 558 DeviceState parent; 559 uint32_t liobn; 560 uint32_t nb_table; 561 uint64_t bus_offset; 562 uint32_t page_shift; 563 uint64_t *table; 564 bool bypass; 565 bool vfio_accel; 566 int fd; 567 MemoryRegion iommu; 568 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 569 QLIST_ENTRY(sPAPRTCETable) list; 570 }; 571 572 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 573 574 struct sPAPREventLogEntry { 575 int log_type; 576 bool exception; 577 void *data; 578 QTAILQ_ENTRY(sPAPREventLogEntry) next; 579 }; 580 581 void spapr_events_init(sPAPRMachineState *sm); 582 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 583 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 584 target_ulong addr, target_ulong size, 585 bool cpu_update, bool memory_update); 586 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 587 uint64_t bus_offset, 588 uint32_t page_shift, 589 uint32_t nb_table, 590 bool vfio_accel); 591 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 592 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 593 uint32_t liobn, uint64_t window, uint32_t size); 594 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 595 sPAPRTCETable *tcet); 596 void spapr_pci_switch_vga(bool big_endian); 597 void spapr_hotplug_req_add_event(sPAPRDRConnector *drc); 598 void spapr_hotplug_req_remove_event(sPAPRDRConnector *drc); 599 600 /* rtas-configure-connector state */ 601 struct sPAPRConfigureConnectorState { 602 uint32_t drc_index; 603 int fdt_offset; 604 int fdt_depth; 605 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 606 }; 607 608 void spapr_ccs_reset_hook(void *opaque); 609 610 #define TYPE_SPAPR_RTC "spapr-rtc" 611 612 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 613 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 614 615 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 616 617 /* 618 * This defines the maximum number of DIMM slots we can have for sPAPR 619 * guest. This is not defined by sPAPR but we are defining it to 32 slots 620 * based on default number of slots provided by PowerPC kernel. 621 */ 622 #define SPAPR_MAX_RAM_SLOTS 32 623 624 /* 1GB alignment for hotplug memory region */ 625 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 626 627 /* 628 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 629 * property under ibm,dynamic-reconfiguration-memory node. 630 */ 631 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 632 633 /* 634 * This flag value defines the LMB as assigned in ibm,dynamic-memory 635 * property under ibm,dynamic-reconfiguration-memory node. 636 */ 637 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 638 639 #endif /* !defined (__HW_SPAPR_H__) */ 640