10d09e41aSPaolo Bonzini #if !defined(__HW_SPAPR_H__) 20d09e41aSPaolo Bonzini #define __HW_SPAPR_H__ 30d09e41aSPaolo Bonzini 40d09e41aSPaolo Bonzini #include "sysemu/dma.h" 50d09e41aSPaolo Bonzini #include "hw/ppc/xics.h" 60d09e41aSPaolo Bonzini 70d09e41aSPaolo Bonzini struct VIOsPAPRBus; 80d09e41aSPaolo Bonzini struct sPAPRPHBState; 90d09e41aSPaolo Bonzini struct sPAPRNVRAM; 100d09e41aSPaolo Bonzini 114be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 124be21d56SDavid Gibson 130d09e41aSPaolo Bonzini typedef struct sPAPREnvironment { 140d09e41aSPaolo Bonzini struct VIOsPAPRBus *vio_bus; 150d09e41aSPaolo Bonzini QLIST_HEAD(, sPAPRPHBState) phbs; 160d09e41aSPaolo Bonzini struct sPAPRNVRAM *nvram; 17c04d6cfaSAnthony Liguori XICSState *icp; 1828df36a1SDavid Gibson DeviceState *rtc; 190d09e41aSPaolo Bonzini 200d09e41aSPaolo Bonzini hwaddr ram_limit; 210d09e41aSPaolo Bonzini void *htab; 224be21d56SDavid Gibson uint32_t htab_shift; 230d09e41aSPaolo Bonzini hwaddr rma_size; 240d09e41aSPaolo Bonzini int vrma_adjust; 250d09e41aSPaolo Bonzini hwaddr fdt_addr, rtas_addr; 26b7d1f77aSBenjamin Herrenschmidt ssize_t rtas_size; 27b7d1f77aSBenjamin Herrenschmidt void *rtas_blob; 280d09e41aSPaolo Bonzini void *fdt_skel; 290d09e41aSPaolo Bonzini target_ulong entry_point; 30880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 3198a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 320d09e41aSPaolo Bonzini bool has_graphics; 330d09e41aSPaolo Bonzini 340d09e41aSPaolo Bonzini uint32_t epow_irq; 350d09e41aSPaolo Bonzini Notifier epow_notifier; 364be21d56SDavid Gibson 374be21d56SDavid Gibson /* Migration state */ 384be21d56SDavid Gibson int htab_save_index; 394be21d56SDavid Gibson bool htab_first_pass; 40e68cb8b4SAlexey Kardashevskiy int htab_fd; 4101a57972SSamuel Mendoza-Jonas bool htab_fd_stale; 420d09e41aSPaolo Bonzini } sPAPREnvironment; 430d09e41aSPaolo Bonzini 440d09e41aSPaolo Bonzini #define H_SUCCESS 0 450d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 460d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 470d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 480d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 490d09e41aSPaolo Bonzini #define H_PARTIAL 5 500d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 510d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 520d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 530d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 540d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 550d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 560d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 570d09e41aSPaolo Bonzini is a good time to retry */ 580d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 590d09e41aSPaolo Bonzini is a good time to retry */ 600d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 610d09e41aSPaolo Bonzini is a good time to retry */ 620d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 630d09e41aSPaolo Bonzini is a good time to retry */ 640d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 650d09e41aSPaolo Bonzini is a good time to retry */ 660d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 670d09e41aSPaolo Bonzini is a good time to retry */ 680d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 690d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 700d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 710d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 720d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 730d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 740d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 750d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 760d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 770d09e41aSPaolo Bonzini #define H_NO_MEM -9 780d09e41aSPaolo Bonzini #define H_AUTHORITY -10 790d09e41aSPaolo Bonzini #define H_PERMISSION -11 800d09e41aSPaolo Bonzini #define H_DROPPED -12 810d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 820d09e41aSPaolo Bonzini #define H_DEST_PARM -14 830d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 840d09e41aSPaolo Bonzini #define H_RESOURCE -16 850d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 860d09e41aSPaolo Bonzini #define H_RH_PARM -18 870d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 880d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 890d09e41aSPaolo Bonzini #define H_EQ_PARM -21 900d09e41aSPaolo Bonzini #define H_RT_PARM -22 910d09e41aSPaolo Bonzini #define H_ST_PARM -23 920d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 930d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 940d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 950d09e41aSPaolo Bonzini #define H_MEM_PARM -28 960d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 970d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 980d09e41aSPaolo Bonzini #define H_PORT_PARM -31 990d09e41aSPaolo Bonzini #define H_MCG_PARM -32 1000d09e41aSPaolo Bonzini #define H_VL_PARM -33 1010d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 1020d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 1030d09e41aSPaolo Bonzini 1040d09e41aSPaolo Bonzini #define H_MASK_PARM -37 1050d09e41aSPaolo Bonzini #define H_MCG_FULL -38 1060d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 1070d09e41aSPaolo Bonzini #define H_P_COUNTER -40 1080d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 1090d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 1100d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 1110d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 1120d09e41aSPaolo Bonzini #define H_R_STATE -45 1130d09e41aSPaolo Bonzini #define H_RESCINDEND -46 11442561bf2SAnton Blanchard #define H_P2 -55 11542561bf2SAnton Blanchard #define H_P3 -56 11642561bf2SAnton Blanchard #define H_P4 -57 11742561bf2SAnton Blanchard #define H_P5 -58 11842561bf2SAnton Blanchard #define H_P6 -59 11942561bf2SAnton Blanchard #define H_P7 -60 12042561bf2SAnton Blanchard #define H_P8 -61 12142561bf2SAnton Blanchard #define H_P9 -62 12242561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 1230d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 1240d09e41aSPaolo Bonzini 1250d09e41aSPaolo Bonzini 1260d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 1270d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 1280d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 1290d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 1300d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 1310d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 1320d09e41aSPaolo Bonzini * way to check for the long_busy return codes 1330d09e41aSPaolo Bonzini */ 1340d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 1350d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 1360d09e41aSPaolo Bonzini 1370d09e41aSPaolo Bonzini /* Flags */ 1380d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 1390d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 1400d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 1410d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 1420d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 1430d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 1440d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 1450d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 1460d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 1470d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 1480d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 1490d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 1500d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 1510d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 1520d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 1530d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 1540d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 1550d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 1560d09e41aSPaolo Bonzini 157a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 158a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 159a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 160a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 161a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 162a46622fdSAlexey Kardashevskiy 163a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 16442561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 16542561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 16642561bf2SAnton Blanchard 167d5ac4f54SAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 168d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_NONE 0 169d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_0001_8000 2 170d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 171d5ac4f54SAlexey Kardashevskiy 1720d09e41aSPaolo Bonzini /* VASI States */ 1730d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 1740d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 1750d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 1760d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 1770d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 1780d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 1790d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 1800d09e41aSPaolo Bonzini 1810d09e41aSPaolo Bonzini /* DABRX flags */ 1820d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 1830d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 1840d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 1850d09e41aSPaolo Bonzini 1860d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 1870d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 1880d09e41aSPaolo Bonzini 1890d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 1900d09e41aSPaolo Bonzini #define H_REMOVE 0x04 1910d09e41aSPaolo Bonzini #define H_ENTER 0x08 1920d09e41aSPaolo Bonzini #define H_READ 0x0c 1930d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 1940d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 1950d09e41aSPaolo Bonzini #define H_PROTECT 0x18 1960d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 1970d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 1980d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 1990d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 2000d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 2010d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 2020d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 2030d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 2040d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 2050d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 2060d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 2070d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 2080d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 2090d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 2100d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 2110d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 2120d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 2130d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 2140d09e41aSPaolo Bonzini #define H_EOI 0x64 2150d09e41aSPaolo Bonzini #define H_CPPR 0x68 2160d09e41aSPaolo Bonzini #define H_IPI 0x6c 2170d09e41aSPaolo Bonzini #define H_IPOLL 0x70 2180d09e41aSPaolo Bonzini #define H_XIRR 0x74 2190d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 2200d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 2210d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 2220d09e41aSPaolo Bonzini #define H_CEDE 0xE0 2230d09e41aSPaolo Bonzini #define H_CONFER 0xE4 2240d09e41aSPaolo Bonzini #define H_PROD 0xE8 2250d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 2260d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 2270d09e41aSPaolo Bonzini #define H_PURR 0xF4 2280d09e41aSPaolo Bonzini #define H_PIC 0xF8 2290d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 2300d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 2310d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 2320d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 2330d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 2340d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 2350d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 2360d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 2370d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 2380d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 2390d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 2400d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 2410d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 2420d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 2430d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 2440d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 2450d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 2460d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 2470d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 2480d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 2490d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 2500d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 2510d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 2520d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 2530d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 2540d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 2550d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 2560d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 2570d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 2580d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 2590d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 2600d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 2610d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 2620d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 2630d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 2640d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 2650d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 2660d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 2670d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 2680d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 2690d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 2700d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 2710d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 2720d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 2730d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 2740d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 2750d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 2760d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 2770d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 2780d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 2790d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 2800d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 2810d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 2820d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 2830d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 2840d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 2850d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 2860d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 2870d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 2880d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 2890d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 2900d09e41aSPaolo Bonzini #define H_JOIN 0x298 2910d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 2920d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 2930d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 2940d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 2950d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 2965d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 29742561bf2SAnton Blanchard #define H_SET_MODE 0x31C 29842561bf2SAnton Blanchard #define MAX_HCALL_OPCODE H_SET_MODE 2990d09e41aSPaolo Bonzini 3000d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 3010d09e41aSPaolo Bonzini * as well. 3020d09e41aSPaolo Bonzini * 3030d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 3040d09e41aSPaolo Bonzini * So far we just need one for H_RTAS, but in future we'll need more 3050d09e41aSPaolo Bonzini * for extensions like virtio. We put those into the 0xf000-0xfffc 3060d09e41aSPaolo Bonzini * range which is reserved by PAPR for "platform-specific" hcalls. 3070d09e41aSPaolo Bonzini */ 3080d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 3090d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 3100d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 3112a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 3122a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 3132a6593cbSAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 3140d09e41aSPaolo Bonzini 3150d09e41aSPaolo Bonzini extern sPAPREnvironment *spapr; 3160d09e41aSPaolo Bonzini 3172a6593cbSAlexey Kardashevskiy typedef struct sPAPRDeviceTreeUpdateHeader { 3182a6593cbSAlexey Kardashevskiy uint32_t version_id; 3192a6593cbSAlexey Kardashevskiy } sPAPRDeviceTreeUpdateHeader; 3202a6593cbSAlexey Kardashevskiy 3210d09e41aSPaolo Bonzini /*#define DEBUG_SPAPR_HCALLS*/ 3220d09e41aSPaolo Bonzini 3230d09e41aSPaolo Bonzini #ifdef DEBUG_SPAPR_HCALLS 3240d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 3250d09e41aSPaolo Bonzini do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) 3260d09e41aSPaolo Bonzini #else 3270d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 3280d09e41aSPaolo Bonzini do { } while (0) 3290d09e41aSPaolo Bonzini #endif 3300d09e41aSPaolo Bonzini 3310d09e41aSPaolo Bonzini typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 3320d09e41aSPaolo Bonzini target_ulong opcode, 3330d09e41aSPaolo Bonzini target_ulong *args); 3340d09e41aSPaolo Bonzini 3350d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 3360d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 3370d09e41aSPaolo Bonzini target_ulong *args); 3380d09e41aSPaolo Bonzini 3390d09e41aSPaolo Bonzini int spapr_allocate_irq(int hint, bool lsi); 340f1c2dc7cSAlexey Kardashevskiy int spapr_allocate_irq_block(int num, bool lsi, bool msi); 3410d09e41aSPaolo Bonzini 342ee954280SGavin Shan /* ibm,set-eeh-option */ 343ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 344ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 345ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 346ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 347ee954280SGavin Shan 348ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 349ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 350ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 351ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 352ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 353ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 354ee954280SGavin Shan 355ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 356ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 357ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 358ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 359ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 360ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 361ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 362ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 363ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 364ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 365ee954280SGavin Shan 366ee954280SGavin Shan /* ibm,set-slot-reset */ 367ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 368ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 369ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 370ee954280SGavin Shan 371ee954280SGavin Shan /* ibm,slot-error-detail */ 372ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 373ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 374ee954280SGavin Shan 375a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 376a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 377a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 378a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 379a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 380a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 3813ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 3823ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 383a64d325dSAlexey Kardashevskiy 3843a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 3853a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 3863a3b8502SAlexey Kardashevskiy 3873a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 3883a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 3893a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 3903a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 3913a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 3923a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 3933a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 3943a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 3953a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 3963a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 3973a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 3983a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 3993a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 4003a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 4013a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 4023a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 4033a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 4043a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 4053a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 4063a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 4073a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 4083a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 4093a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 4103a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 4113a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 4123a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 4133a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 4143a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 4153a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 4163a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 4173a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 4183a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 419ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 420ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 421ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 422ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 423ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 424ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 4253a3b8502SAlexey Kardashevskiy 426ee954280SGavin Shan #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) 4273a3b8502SAlexey Kardashevskiy 4283052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 4293b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 4303052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 431b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 4323052d951SSam bobroff 4333052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 4343052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 4353052d951SSam bobroff */ 4363052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 4373052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 4383052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 4393052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 4403052d951SSam bobroff 4414fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 4424fe822e0SAlexey Kardashevskiy { 4434fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 4444fe822e0SAlexey Kardashevskiy } 4454fe822e0SAlexey Kardashevskiy 4460d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 4470d09e41aSPaolo Bonzini { 448fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 4490d09e41aSPaolo Bonzini } 4500d09e41aSPaolo Bonzini 4510d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 4520d09e41aSPaolo Bonzini { 453ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 4540d09e41aSPaolo Bonzini } 4550d09e41aSPaolo Bonzini 456ce3fa1ecSSam bobroff 457ce3fa1ecSSam bobroff static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, 458ce3fa1ecSSam bobroff uint8_t *buffer, uint16_t buffer_len) 459ce3fa1ecSSam bobroff { 460ce3fa1ecSSam bobroff if (phys_len < 2) { 461ce3fa1ecSSam bobroff return; 462ce3fa1ecSSam bobroff } 463ce3fa1ecSSam bobroff stw_be_phys(&address_space_memory, 464ce3fa1ecSSam bobroff ppc64_phys_to_real(phys), buffer_len); 465ce3fa1ecSSam bobroff cpu_physical_memory_write(ppc64_phys_to_real(phys + 2), 466ce3fa1ecSSam bobroff buffer, MIN(buffer_len, phys_len - 2)); 467ce3fa1ecSSam bobroff } 468ce3fa1ecSSam bobroff 469210b580bSAnthony Liguori typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 470210b580bSAnthony Liguori uint32_t token, 4710d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 4720d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 4733a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 474210b580bSAnthony Liguori target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, 4750d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 4760d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 4770d09e41aSPaolo Bonzini int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 4780d09e41aSPaolo Bonzini hwaddr rtas_size); 4790d09e41aSPaolo Bonzini 4800d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 4810d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 4820d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 4830d09e41aSPaolo Bonzini 4840d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 4854290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 486c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 487c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 488*d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 489c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 4900d09e41aSPaolo Bonzini 4910d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 4920d09e41aSPaolo Bonzini 4932b7dc949SPaolo Bonzini typedef struct sPAPRTCETable sPAPRTCETable; 4940d09e41aSPaolo Bonzini 495a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 496a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 497a83000f5SAnthony Liguori OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 498a83000f5SAnthony Liguori 499a83000f5SAnthony Liguori struct sPAPRTCETable { 500a83000f5SAnthony Liguori DeviceState parent; 501a83000f5SAnthony Liguori uint32_t liobn; 502a83000f5SAnthony Liguori uint32_t nb_table; 5031b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 504650f33adSAlexey Kardashevskiy uint32_t page_shift; 505a83000f5SAnthony Liguori uint64_t *table; 506a83000f5SAnthony Liguori bool bypass; 5079bb62a07SAlexey Kardashevskiy bool vfio_accel; 508a83000f5SAnthony Liguori int fd; 509a83000f5SAnthony Liguori MemoryRegion iommu; 510ee9a569aSAlexey Kardashevskiy struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 511a83000f5SAnthony Liguori QLIST_ENTRY(sPAPRTCETable) list; 512a83000f5SAnthony Liguori }; 513a83000f5SAnthony Liguori 5140d09e41aSPaolo Bonzini void spapr_events_init(sPAPREnvironment *spapr); 5150d09e41aSPaolo Bonzini void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 5162a6593cbSAlexey Kardashevskiy int spapr_h_cas_compose_response(target_ulong addr, target_ulong size); 51784af6d9fSPaolo Bonzini sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 5181b8eceeeSAlexey Kardashevskiy uint64_t bus_offset, 519650f33adSAlexey Kardashevskiy uint32_t page_shift, 5209bb62a07SAlexey Kardashevskiy uint32_t nb_table, 5219bb62a07SAlexey Kardashevskiy bool vfio_accel); 522a84bb436SPaolo Bonzini MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 5230d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 5240d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 5250d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 5262b7dc949SPaolo Bonzini sPAPRTCETable *tcet); 527eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 52828df36a1SDavid Gibson 52928df36a1SDavid Gibson #define TYPE_SPAPR_RTC "spapr-rtc" 53028df36a1SDavid Gibson 53128df36a1SDavid Gibson void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 532880ae7deSDavid Gibson int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 5330d09e41aSPaolo Bonzini 5340d09e41aSPaolo Bonzini #endif /* !defined (__HW_SPAPR_H__) */ 535