12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11*ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 120d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 130d09e41aSPaolo Bonzini 14*ce2918cbSDavid Gibson struct SpaprVioBus; 15*ce2918cbSDavid Gibson struct SpaprPhbState; 16*ce2918cbSDavid Gibson struct SpaprNvram; 170d8d6a24SThomas Huth 18*ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 19*ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 20*ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 210d09e41aSPaolo Bonzini 224be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 231b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 244be21d56SDavid Gibson 25afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 26afd10a0fSBharata B Rao 27147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 28147ff807SCédric Le Goater 29147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 30*ce2918cbSDavid Gibson OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 31147ff807SCédric Le Goater 32*ce2918cbSDavid Gibson typedef struct SpaprRtcState SpaprRtcState; 33*ce2918cbSDavid Gibson struct SpaprRtcState { 34147ff807SCédric Le Goater /*< private >*/ 35147ff807SCédric Le Goater DeviceState parent_obj; 36147ff807SCédric Le Goater int64_t ns_offset; 37147ff807SCédric Le Goater }; 38147ff807SCédric Le Goater 39*ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 40*ce2918cbSDavid Gibson typedef struct SpaprMachineClass SpaprMachineClass; 4128e02042SDavid Gibson 4228e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 4328e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 44*ce2918cbSDavid Gibson OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 45183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 46*ce2918cbSDavid Gibson OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 47183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 48*ce2918cbSDavid Gibson OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 49183930c0SDavid Gibson 5030f4b05bSDavid Gibson typedef enum { 5130f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5230f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5430f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 55*ce2918cbSDavid Gibson } SpaprResizeHpt; 5630f4b05bSDavid Gibson 57183930c0SDavid Gibson /** 5833face6bSDavid Gibson * Capabilities 5933face6bSDavid Gibson */ 6033face6bSDavid Gibson 61ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 624e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6329386642SDavid Gibson /* Vector Scalar Extensions */ 644e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 652d1fb9bcSDavid Gibson /* Decimal Floating Point */ 664e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 678f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 688f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 6909114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 7009114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 714be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 724be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 732309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 742309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 75b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 76b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 77c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 78c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 798ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 808ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 814e5fe368SSuraj Jitindar Singh /* Num Caps */ 828ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) 834e5fe368SSuraj Jitindar Singh 844e5fe368SSuraj Jitindar Singh /* 854e5fe368SSuraj Jitindar Singh * Capability Values 864e5fe368SSuraj Jitindar Singh */ 874e5fe368SSuraj Jitindar Singh /* Bool Caps */ 884e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 894e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 90399b2896SSuraj Jitindar Singh 91c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 92399b2896SSuraj Jitindar Singh 93399b2896SSuraj Jitindar Singh /* Generic */ 946898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 956898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 966898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 97399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 98c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 99c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 100399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1012d1fb9bcSDavid Gibson 102*ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 103*ce2918cbSDavid Gibson struct SpaprCapabilities { 1044e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 10533face6bSDavid Gibson }; 10633face6bSDavid Gibson 10733face6bSDavid Gibson /** 108*ce2918cbSDavid Gibson * SpaprMachineClass: 109183930c0SDavid Gibson */ 110*ce2918cbSDavid Gibson struct SpaprMachineClass { 111183930c0SDavid Gibson /*< private >*/ 112183930c0SDavid Gibson MachineClass parent_class; 113183930c0SDavid Gibson 114183930c0SDavid Gibson /*< public >*/ 115224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 116962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 117fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 11857040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 11946f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 12082cffa2eSCédric Le Goater bool legacy_irq_allocation; 12182cffa2eSCédric Le Goater 122*ce2918cbSDavid Gibson void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 123daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 124daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 1256737d9adSDavid Gibson unsigned n_dma, uint32_t *liobns, Error **errp); 126*ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 127*ce2918cbSDavid Gibson SpaprCapabilities default_caps; 128*ce2918cbSDavid Gibson SpaprIrq *irq; 129183930c0SDavid Gibson }; 13028e02042SDavid Gibson 13128e02042SDavid Gibson /** 132*ce2918cbSDavid Gibson * SpaprMachineState: 13328e02042SDavid Gibson */ 134*ce2918cbSDavid Gibson struct SpaprMachineState { 13528e02042SDavid Gibson /*< private >*/ 13628e02042SDavid Gibson MachineState parent_obj; 13728e02042SDavid Gibson 138*ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 139*ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 140*ce2918cbSDavid Gibson struct SpaprNvram *nvram; 141681bfadeSCédric Le Goater ICSState *ics; 142*ce2918cbSDavid Gibson SpaprRtcState rtc; 1430d09e41aSPaolo Bonzini 144*ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1450d09e41aSPaolo Bonzini void *htab; 1464be21d56SDavid Gibson uint32_t htab_shift; 1479861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 148*ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1490b0b8310SDavid Gibson 1500d09e41aSPaolo Bonzini hwaddr rma_size; 1510d09e41aSPaolo Bonzini int vrma_adjust; 152b7d1f77aSBenjamin Herrenschmidt ssize_t rtas_size; 153b7d1f77aSBenjamin Herrenschmidt void *rtas_blob; 154fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 155fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 156fea35ca4SAlexey Kardashevskiy void *fdt_blob; 157a19f7fb0SDavid Gibson long kernel_size; 158a19f7fb0SDavid Gibson bool kernel_le; 159a19f7fb0SDavid Gibson uint32_t initrd_base; 160a19f7fb0SDavid Gibson long initrd_size; 161880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 16298a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1630d09e41aSPaolo Bonzini bool has_graphics; 164fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1650d09e41aSPaolo Bonzini 1660d09e41aSPaolo Bonzini Notifier epow_notifier; 167*ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 168ffbb1705SMichael Roth bool use_hotplug_event_source; 169*ce2918cbSDavid Gibson SpaprEventSource *event_sources; 1704be21d56SDavid Gibson 1717843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 1727843c0d6SDavid Gibson bool cas_reboot; 1737843c0d6SDavid Gibson bool cas_legacy_guest_workaround; 174*ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 175*ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1767843c0d6SDavid Gibson uint32_t max_compat_pvr; 1777843c0d6SDavid Gibson 1784be21d56SDavid Gibson /* Migration state */ 1794be21d56SDavid Gibson int htab_save_index; 1804be21d56SDavid Gibson bool htab_first_pass; 181e68cb8b4SAlexey Kardashevskiy int htab_fd; 18246503c2bSMichael Roth 1830cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1840cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1850cffce56SDavid Gibson * occurs during the unplug process. */ 186*ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 1870cffce56SDavid Gibson 18828e02042SDavid Gibson /*< public >*/ 18928e02042SDavid Gibson char *kvm_type; 19027461d69SPrasad J Pandit char *host_model; 19127461d69SPrasad J Pandit char *host_serial; 192852ad27eSCédric Le Goater 19382cffa2eSCédric Le Goater int32_t irq_map_nr; 19482cffa2eSCédric Le Goater unsigned long *irq_map; 195*ce2918cbSDavid Gibson SpaprXive *xive; 196*ce2918cbSDavid Gibson SpaprIrq *irq; 197872ff3deSCédric Le Goater qemu_irq *qirqs; 19833face6bSDavid Gibson 1994e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 200*ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 20128e02042SDavid Gibson }; 2020d09e41aSPaolo Bonzini 2030d09e41aSPaolo Bonzini #define H_SUCCESS 0 2040d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2050d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2060d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2070d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2080d09e41aSPaolo Bonzini #define H_PARTIAL 5 2090d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2100d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2110d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2120d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2130d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2140d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2150d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2160d09e41aSPaolo Bonzini is a good time to retry */ 2170d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2180d09e41aSPaolo Bonzini is a good time to retry */ 2190d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2200d09e41aSPaolo Bonzini is a good time to retry */ 2210d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2220d09e41aSPaolo Bonzini is a good time to retry */ 2230d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2240d09e41aSPaolo Bonzini is a good time to retry */ 2250d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2260d09e41aSPaolo Bonzini is a good time to retry */ 2270d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2280d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2290d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2300d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2310d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2320d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2330d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2340d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2350d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2360d09e41aSPaolo Bonzini #define H_NO_MEM -9 2370d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2380d09e41aSPaolo Bonzini #define H_PERMISSION -11 2390d09e41aSPaolo Bonzini #define H_DROPPED -12 2400d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2410d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2420d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2430d09e41aSPaolo Bonzini #define H_RESOURCE -16 2440d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2450d09e41aSPaolo Bonzini #define H_RH_PARM -18 2460d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2470d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2480d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2490d09e41aSPaolo Bonzini #define H_RT_PARM -22 2500d09e41aSPaolo Bonzini #define H_ST_PARM -23 2510d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 2520d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 2530d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 2540d09e41aSPaolo Bonzini #define H_MEM_PARM -28 2550d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 2560d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 2570d09e41aSPaolo Bonzini #define H_PORT_PARM -31 2580d09e41aSPaolo Bonzini #define H_MCG_PARM -32 2590d09e41aSPaolo Bonzini #define H_VL_PARM -33 2600d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 2610d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 2620d09e41aSPaolo Bonzini 2630d09e41aSPaolo Bonzini #define H_MASK_PARM -37 2640d09e41aSPaolo Bonzini #define H_MCG_FULL -38 2650d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 2660d09e41aSPaolo Bonzini #define H_P_COUNTER -40 2670d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 2680d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 2690d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 2700d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 2710d09e41aSPaolo Bonzini #define H_R_STATE -45 2720d09e41aSPaolo Bonzini #define H_RESCINDEND -46 27342561bf2SAnton Blanchard #define H_P2 -55 27442561bf2SAnton Blanchard #define H_P3 -56 27542561bf2SAnton Blanchard #define H_P4 -57 27642561bf2SAnton Blanchard #define H_P5 -58 27742561bf2SAnton Blanchard #define H_P6 -59 27842561bf2SAnton Blanchard #define H_P7 -60 27942561bf2SAnton Blanchard #define H_P8 -61 28042561bf2SAnton Blanchard #define H_P9 -62 28142561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 2820d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 2830d09e41aSPaolo Bonzini 2840d09e41aSPaolo Bonzini 2850d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 2860d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 2870d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 2880d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 2890d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 2900d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 2910d09e41aSPaolo Bonzini * way to check for the long_busy return codes 2920d09e41aSPaolo Bonzini */ 2930d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 2940d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 2950d09e41aSPaolo Bonzini 2960d09e41aSPaolo Bonzini /* Flags */ 2970d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 2980d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 2990d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3000d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3010d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3020d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3030d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3040d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3050d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3060d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3070d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3080d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3090d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3100d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3110d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3120d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3130d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3140d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3150d09e41aSPaolo Bonzini 316a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 317a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 318a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 319a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 320a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 321a46622fdSAlexey Kardashevskiy 322a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 32342561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 32442561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 32542561bf2SAnton Blanchard 3260d09e41aSPaolo Bonzini /* VASI States */ 3270d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3280d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3290d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3300d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3310d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3320d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3330d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3340d09e41aSPaolo Bonzini 3350d09e41aSPaolo Bonzini /* DABRX flags */ 3360d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3370d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3380d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3390d09e41aSPaolo Bonzini 3408acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3418acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3428acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3438acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3448acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3458acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3468acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3478acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 348c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 349399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 3508acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 3518acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 3528acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 353399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 3548acc2ae5SSuraj Jitindar Singh 3550d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 3560d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 3570d09e41aSPaolo Bonzini 3580d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 3590d09e41aSPaolo Bonzini #define H_REMOVE 0x04 3600d09e41aSPaolo Bonzini #define H_ENTER 0x08 3610d09e41aSPaolo Bonzini #define H_READ 0x0c 3620d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 3630d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 3640d09e41aSPaolo Bonzini #define H_PROTECT 0x18 3650d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 3660d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 3670d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 3680d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 3690d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 3700d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 3710d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 3720d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 3730d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 3740d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 3750d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 3760d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 3770d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 3780d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 3790d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 3800d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 3810d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 3820d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 3830d09e41aSPaolo Bonzini #define H_EOI 0x64 3840d09e41aSPaolo Bonzini #define H_CPPR 0x68 3850d09e41aSPaolo Bonzini #define H_IPI 0x6c 3860d09e41aSPaolo Bonzini #define H_IPOLL 0x70 3870d09e41aSPaolo Bonzini #define H_XIRR 0x74 3880d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 3890d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 3900d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 3910d09e41aSPaolo Bonzini #define H_CEDE 0xE0 3920d09e41aSPaolo Bonzini #define H_CONFER 0xE4 3930d09e41aSPaolo Bonzini #define H_PROD 0xE8 3940d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 3950d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 3960d09e41aSPaolo Bonzini #define H_PURR 0xF4 3970d09e41aSPaolo Bonzini #define H_PIC 0xF8 3980d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 3990d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4000d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4010d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4020d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4030d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4040d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4050d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4060d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4070d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4080d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4090d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4100d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4110d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4120d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4130d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4140d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4150d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4160d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4170d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4180d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4190d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4200d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4210d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4220d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4230d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4240d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4250d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4260d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4270d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4280d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4290d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4300d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4310d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4320d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4330d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4340d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4350d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4360d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4370d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4380d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4390d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4400d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4410d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 442c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4430d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4440d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4450d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4460d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4470d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4480d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4490d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4500d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 4510d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 4520d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 4530d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 4540d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 4550d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 4560d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 4570d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 4580d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 4590d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 4600d09e41aSPaolo Bonzini #define H_JOIN 0x298 4610d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 4620d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 4630d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 4640d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 4650d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 466c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 4675d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 4684d9392beSThomas Huth #define H_RANDOM 0x300 46942561bf2SAnton Blanchard #define H_SET_MODE 0x31C 47030f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 47130f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 472d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 473d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 474d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 4751c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 47623bcd5ebSCédric Le Goater 47723bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 47823bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 47923bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 48023bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 48123bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 48223bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 48323bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 48423bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 48523bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 48623bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 48723bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 48823bcd5ebSCédric Le Goater 48923bcd5ebSCédric Le Goater #define MAX_HCALL_OPCODE H_INT_RESET 4900d09e41aSPaolo Bonzini 4910d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 4920d09e41aSPaolo Bonzini * as well. 4930d09e41aSPaolo Bonzini * 4940d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 495498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 496498cd995SGreg Kurz * for "platform-specific" hcalls. 4970d09e41aSPaolo Bonzini */ 4980d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 4990d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5000d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5012a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5022a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 503fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 504fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 5050d09e41aSPaolo Bonzini 506*ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 5072a6593cbSAlexey Kardashevskiy uint32_t version_id; 508*ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 5092a6593cbSAlexey Kardashevskiy 5100d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 511aaf87c66SThomas Huth do { \ 512aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 513aaf87c66SThomas Huth } while (0) 5140d09e41aSPaolo Bonzini 515*ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 5160d09e41aSPaolo Bonzini target_ulong opcode, 5170d09e41aSPaolo Bonzini target_ulong *args); 5180d09e41aSPaolo Bonzini 5190d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5200d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5210d09e41aSPaolo Bonzini target_ulong *args); 5220d09e41aSPaolo Bonzini 523ee954280SGavin Shan /* ibm,set-eeh-option */ 524ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 525ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 526ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 527ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 528ee954280SGavin Shan 529ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 530ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 531ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 532ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 533ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 534ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 535ee954280SGavin Shan 536ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 537ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 538ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 539ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 540ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 541ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 542ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 543ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 544ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 545ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 546ee954280SGavin Shan 547ee954280SGavin Shan /* ibm,set-slot-reset */ 548ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 549ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 550ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 551ee954280SGavin Shan 552ee954280SGavin Shan /* ibm,slot-error-detail */ 553ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 554ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 555ee954280SGavin Shan 556a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 557a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 558a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 559a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 560a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 561a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 5623ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 5639d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 5643ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 565c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 566a64d325dSAlexey Kardashevskiy 567ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 568ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 569ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 570ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 571ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 572ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 573ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 574ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 575ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 576ae4de14cSAlexey Kardashevskiy 5773a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 5783a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 5793a3b8502SAlexey Kardashevskiy 5803a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 5813a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 5823a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 5833a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 5843a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 5853a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 5863a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 5873a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 5883a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 5893a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 5903a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 5913a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 5923a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 5933a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 5943a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 5953a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 5963a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 5973a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 5983a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 5993a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 6003a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 6013a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 6023a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 6033a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 6043a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 6053a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 6063a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 6073a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 6083a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 6093a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 6103a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6113a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 612ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 613ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 614ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 615ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 616ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 617ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 618ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 619ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 620ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 621ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 6223a3b8502SAlexey Kardashevskiy 623ae4de14cSAlexey Kardashevskiy #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 6243a3b8502SAlexey Kardashevskiy 6253052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 6263b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 6273052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 628b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 6293052d951SSam bobroff 6308c8639dfSMike Day /* RTAS indicator/sensor types 6318c8639dfSMike Day * 6328c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 6338c8639dfSMike Day * 6348c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 6358c8639dfSMike Day */ 6368c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 6378c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 6388c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 6398c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 6408c8639dfSMike Day 6413052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 6423052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 6433052d951SSam bobroff */ 6443052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 6453052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 6463052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 6473052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 6483052d951SSam bobroff 6494fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 6504fe822e0SAlexey Kardashevskiy { 6514fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 6524fe822e0SAlexey Kardashevskiy } 6534fe822e0SAlexey Kardashevskiy 6540d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 6550d09e41aSPaolo Bonzini { 656fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 6570d09e41aSPaolo Bonzini } 6580d09e41aSPaolo Bonzini 659a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 660a14aa92bSGavin Shan { 661a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 662a14aa92bSGavin Shan } 663a14aa92bSGavin Shan 6640d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 6650d09e41aSPaolo Bonzini { 666ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 6670d09e41aSPaolo Bonzini } 6680d09e41aSPaolo Bonzini 669*ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 670210b580bSAnthony Liguori uint32_t token, 6710d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 6720d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 6733a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 674*ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 6750d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 6760d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 6773f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 678*ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 6790d09e41aSPaolo Bonzini 6800d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 6810d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 6820d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 6830d09e41aSPaolo Bonzini 6840d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 6854290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 686c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 687c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 688d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 689c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 6900d09e41aSPaolo Bonzini 6910d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 6920d09e41aSPaolo Bonzini 69379853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 69479853e18STyrel Datwyler 695bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 696bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 697bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 698bb2d8ab6SGreg Kurz */ 6995c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 700bb2d8ab6SGreg Kurz { 701bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 702bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 703bb2d8ab6SGreg Kurz } 704bb2d8ab6SGreg Kurz 705*ce2918cbSDavid Gibson typedef struct SpaprTceTable SpaprTceTable; 7060d09e41aSPaolo Bonzini 707a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 708a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 709*ce2918cbSDavid Gibson OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 710a83000f5SAnthony Liguori 7111221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 7121221a474SAlexey Kardashevskiy #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 7131221a474SAlexey Kardashevskiy OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 7141221a474SAlexey Kardashevskiy 715*ce2918cbSDavid Gibson struct SpaprTceTable { 716a83000f5SAnthony Liguori DeviceState parent; 717a83000f5SAnthony Liguori uint32_t liobn; 718a83000f5SAnthony Liguori uint32_t nb_table; 7191b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 720650f33adSAlexey Kardashevskiy uint32_t page_shift; 721a83000f5SAnthony Liguori uint64_t *table; 722a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 723a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 724a83000f5SAnthony Liguori bool bypass; 7256a81dd17SDavid Gibson bool need_vfio; 7265f366667SAlexey Kardashevskiy bool skipping_replay; 727a83000f5SAnthony Liguori int fd; 7283df9d748SAlexey Kardashevskiy MemoryRegion root; 7293df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 730*ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 731*ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 732a83000f5SAnthony Liguori }; 733a83000f5SAnthony Liguori 734*ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 73531fe14d1SNathan Fontenot 736*ce2918cbSDavid Gibson struct SpaprEventLogEntry { 737fd38804bSDaniel Henrique Barboza uint32_t summary; 738fd38804bSDaniel Henrique Barboza uint32_t extended_length; 739fd38804bSDaniel Henrique Barboza void *extended_log; 740*ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 74131fe14d1SNathan Fontenot }; 74231fe14d1SNathan Fontenot 743*ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 744*ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 745*ce2918cbSDavid Gibson int spapr_h_cas_compose_response(SpaprMachineState *sm, 74603d196b7SBharata B Rao target_ulong addr, target_ulong size, 747*ce2918cbSDavid Gibson SpaprOptionVector *ov5_updates); 748*ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 749*ce2918cbSDavid Gibson void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); 750*ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 751*ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 752*ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 753df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 754df7625d4SAlexey Kardashevskiy uint32_t nb_table); 755*ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 756*ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 757c10325d6SDavid Gibson 758*ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 7590d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 7600d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 7610d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 762*ce2918cbSDavid Gibson SpaprTceTable *tcet); 763eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 764*ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 765*ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 766*ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 7677a36ae7aSBharata B Rao uint32_t count); 768*ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 7697a36ae7aSBharata B Rao uint32_t count); 770*ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 771afdbd403SBharata B Rao uint32_t count, uint32_t index); 772*ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 773afdbd403SBharata B Rao uint32_t count, uint32_t index); 7740b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 775*ce2918cbSDavid Gibson void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 7762772cf6bSDavid Gibson Error **errp); 777*ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 778*ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 77928df36a1SDavid Gibson 78062d38c9bSGreg Kurz /* DRC callbacks. */ 78131834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 782*ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 783345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 78431834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 785*ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 78662d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 787bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 788*ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 789bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 79031834723SDaniel Henrique Barboza 791*ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 792*ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 79328df36a1SDavid Gibson 794147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 7950d09e41aSPaolo Bonzini 796e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 797db4ef288SBharata B Rao 7984a1c9cf0SBharata B Rao /* 7994a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 8004a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 8014a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 8024a1c9cf0SBharata B Rao */ 8034a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 8044a1c9cf0SBharata B Rao 805ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 806ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 8074a1c9cf0SBharata B Rao 80803d196b7SBharata B Rao /* 80903d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 81003d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 81103d196b7SBharata B Rao */ 81203d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 81303d196b7SBharata B Rao 81403d196b7SBharata B Rao /* 815d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 816d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 81703d196b7SBharata B Rao */ 81803d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 819d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 820d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 82103d196b7SBharata B Rao 8221c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 8231c7ad77eSNicholas Piggin 8240b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 8250b0b8310SDavid Gibson 82614bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 827648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 8282e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 8292e886fb3SSam Bobroff 8304e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 8314e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 8324e5fe368SSuraj Jitindar Singh 83333face6bSDavid Gibson /* 83433face6bSDavid Gibson * Handling of optional capabilities 83533face6bSDavid Gibson */ 8364e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 8374e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 8384e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 8398f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 84009114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 8414be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 842b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 843c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 8448ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 845be85537dSDavid Gibson 846*ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 84733face6bSDavid Gibson { 8484e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 84933face6bSDavid Gibson } 85033face6bSDavid Gibson 851*ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 852*ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 853*ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 854*ce2918cbSDavid Gibson void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 855*ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 85633face6bSDavid Gibson 857*ce2918cbSDavid Gibson void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 858123eec65SDavid Gibson Error **errp); 859db592b5bSCédric Le Goater /* 860db592b5bSCédric Le Goater * XIVE definitions 861db592b5bSCédric Le Goater */ 862db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 863db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 864db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 865123eec65SDavid Gibson 86600fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 8672a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 868