12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 110d8d6a24SThomas Huth #include "hw/ppc/spapr_xive.h" /* For sPAPRXive */ 120d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 130d09e41aSPaolo Bonzini 140d09e41aSPaolo Bonzini struct VIOsPAPRBus; 150d09e41aSPaolo Bonzini struct sPAPRPHBState; 160d09e41aSPaolo Bonzini struct sPAPRNVRAM; 170d8d6a24SThomas Huth 1831fe14d1SNathan Fontenot typedef struct sPAPREventLogEntry sPAPREventLogEntry; 19ffbb1705SMichael Roth typedef struct sPAPREventSource sPAPREventSource; 200b0b8310SDavid Gibson typedef struct sPAPRPendingHPT sPAPRPendingHPT; 210d09e41aSPaolo Bonzini 224be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 231b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 244be21d56SDavid Gibson 25afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 26afd10a0fSBharata B Rao 27147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 28147ff807SCédric Le Goater 29147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 30147ff807SCédric Le Goater OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 31147ff807SCédric Le Goater 32147ff807SCédric Le Goater typedef struct sPAPRRTCState sPAPRRTCState; 33147ff807SCédric Le Goater struct sPAPRRTCState { 34147ff807SCédric Le Goater /*< private >*/ 35147ff807SCédric Le Goater DeviceState parent_obj; 36147ff807SCédric Le Goater int64_t ns_offset; 37147ff807SCédric Le Goater }; 38147ff807SCédric Le Goater 390cffce56SDavid Gibson typedef struct sPAPRDIMMState sPAPRDIMMState; 40183930c0SDavid Gibson typedef struct sPAPRMachineClass sPAPRMachineClass; 4128e02042SDavid Gibson 4228e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 4328e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 4428e02042SDavid Gibson OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 45183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 46183930c0SDavid Gibson OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 47183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 48183930c0SDavid Gibson OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 49183930c0SDavid Gibson 5030f4b05bSDavid Gibson typedef enum { 5130f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5230f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5430f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 5530f4b05bSDavid Gibson } sPAPRResizeHPT; 5630f4b05bSDavid Gibson 57183930c0SDavid Gibson /** 5833face6bSDavid Gibson * Capabilities 5933face6bSDavid Gibson */ 6033face6bSDavid Gibson 61ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 624e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6329386642SDavid Gibson /* Vector Scalar Extensions */ 644e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 652d1fb9bcSDavid Gibson /* Decimal Floating Point */ 664e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 678f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 688f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 6909114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 7009114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 714be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 724be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 732309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 742309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 75b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 76b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 774e5fe368SSuraj Jitindar Singh /* Num Caps */ 78b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1) 794e5fe368SSuraj Jitindar Singh 804e5fe368SSuraj Jitindar Singh /* 814e5fe368SSuraj Jitindar Singh * Capability Values 824e5fe368SSuraj Jitindar Singh */ 834e5fe368SSuraj Jitindar Singh /* Bool Caps */ 844e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 854e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 86c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 876898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 886898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 896898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 90c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 91c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 922d1fb9bcSDavid Gibson 9333face6bSDavid Gibson typedef struct sPAPRCapabilities sPAPRCapabilities; 9433face6bSDavid Gibson struct sPAPRCapabilities { 954e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 9633face6bSDavid Gibson }; 9733face6bSDavid Gibson 9833face6bSDavid Gibson /** 99183930c0SDavid Gibson * sPAPRMachineClass: 100183930c0SDavid Gibson */ 101183930c0SDavid Gibson struct sPAPRMachineClass { 102183930c0SDavid Gibson /*< private >*/ 103183930c0SDavid Gibson MachineClass parent_class; 104183930c0SDavid Gibson 105183930c0SDavid Gibson /*< public >*/ 106224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 107962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 108fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 10957040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 11046f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 11182cffa2eSCédric Le Goater bool legacy_irq_allocation; 11282cffa2eSCédric Le Goater 1136737d9adSDavid Gibson void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 114daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 115daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 1166737d9adSDavid Gibson unsigned n_dma, uint32_t *liobns, Error **errp); 11730f4b05bSDavid Gibson sPAPRResizeHPT resize_hpt_default; 11833face6bSDavid Gibson sPAPRCapabilities default_caps; 119ef01ed9dSCédric Le Goater sPAPRIrq *irq; 120183930c0SDavid Gibson }; 12128e02042SDavid Gibson 12228e02042SDavid Gibson /** 12328e02042SDavid Gibson * sPAPRMachineState: 12428e02042SDavid Gibson */ 12528e02042SDavid Gibson struct sPAPRMachineState { 12628e02042SDavid Gibson /*< private >*/ 12728e02042SDavid Gibson MachineState parent_obj; 12828e02042SDavid Gibson 1290d09e41aSPaolo Bonzini struct VIOsPAPRBus *vio_bus; 1300d09e41aSPaolo Bonzini QLIST_HEAD(, sPAPRPHBState) phbs; 1310d09e41aSPaolo Bonzini struct sPAPRNVRAM *nvram; 132681bfadeSCédric Le Goater ICSState *ics; 133147ff807SCédric Le Goater sPAPRRTCState rtc; 1340d09e41aSPaolo Bonzini 13530f4b05bSDavid Gibson sPAPRResizeHPT resize_hpt; 1360d09e41aSPaolo Bonzini void *htab; 1374be21d56SDavid Gibson uint32_t htab_shift; 1389861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 1390b0b8310SDavid Gibson sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 1400b0b8310SDavid Gibson 1410d09e41aSPaolo Bonzini hwaddr rma_size; 1420d09e41aSPaolo Bonzini int vrma_adjust; 143b7d1f77aSBenjamin Herrenschmidt ssize_t rtas_size; 144b7d1f77aSBenjamin Herrenschmidt void *rtas_blob; 145fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 146fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 147fea35ca4SAlexey Kardashevskiy void *fdt_blob; 148a19f7fb0SDavid Gibson long kernel_size; 149a19f7fb0SDavid Gibson bool kernel_le; 150a19f7fb0SDavid Gibson uint32_t initrd_base; 151a19f7fb0SDavid Gibson long initrd_size; 152880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 15398a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1540d09e41aSPaolo Bonzini bool has_graphics; 155fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1560d09e41aSPaolo Bonzini 1570d09e41aSPaolo Bonzini Notifier epow_notifier; 15831fe14d1SNathan Fontenot QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 159ffbb1705SMichael Roth bool use_hotplug_event_source; 160ffbb1705SMichael Roth sPAPREventSource *event_sources; 1614be21d56SDavid Gibson 1627843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 1637843c0d6SDavid Gibson bool cas_reboot; 1647843c0d6SDavid Gibson bool cas_legacy_guest_workaround; 1657843c0d6SDavid Gibson sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 1667843c0d6SDavid Gibson sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1677843c0d6SDavid Gibson uint32_t max_compat_pvr; 1687843c0d6SDavid Gibson 1694be21d56SDavid Gibson /* Migration state */ 1704be21d56SDavid Gibson int htab_save_index; 1714be21d56SDavid Gibson bool htab_first_pass; 172e68cb8b4SAlexey Kardashevskiy int htab_fd; 17346503c2bSMichael Roth 1740cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1750cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1760cffce56SDavid Gibson * occurs during the unplug process. */ 1770cffce56SDavid Gibson QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 1780cffce56SDavid Gibson 17928e02042SDavid Gibson /*< public >*/ 18028e02042SDavid Gibson char *kvm_type; 18127461d69SPrasad J Pandit char *host_model; 18227461d69SPrasad J Pandit char *host_serial; 183852ad27eSCédric Le Goater 18482cffa2eSCédric Le Goater int32_t irq_map_nr; 18582cffa2eSCédric Le Goater unsigned long *irq_map; 186dcc345b6SCédric Le Goater sPAPRXive *xive; 1873ba3d0bcSCédric Le Goater sPAPRIrq *irq; 188872ff3deSCédric Le Goater qemu_irq *qirqs; 18933face6bSDavid Gibson 1904e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 1914e5fe368SSuraj Jitindar Singh sPAPRCapabilities def, eff, mig; 19228e02042SDavid Gibson }; 1930d09e41aSPaolo Bonzini 1940d09e41aSPaolo Bonzini #define H_SUCCESS 0 1950d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 1960d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 1970d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 1980d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 1990d09e41aSPaolo Bonzini #define H_PARTIAL 5 2000d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2010d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2020d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2030d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2040d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2050d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2060d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2070d09e41aSPaolo Bonzini is a good time to retry */ 2080d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2090d09e41aSPaolo Bonzini is a good time to retry */ 2100d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2110d09e41aSPaolo Bonzini is a good time to retry */ 2120d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2130d09e41aSPaolo Bonzini is a good time to retry */ 2140d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2150d09e41aSPaolo Bonzini is a good time to retry */ 2160d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2170d09e41aSPaolo Bonzini is a good time to retry */ 2180d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2190d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2200d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2210d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2220d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2230d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2240d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2250d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2260d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2270d09e41aSPaolo Bonzini #define H_NO_MEM -9 2280d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2290d09e41aSPaolo Bonzini #define H_PERMISSION -11 2300d09e41aSPaolo Bonzini #define H_DROPPED -12 2310d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2320d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2330d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2340d09e41aSPaolo Bonzini #define H_RESOURCE -16 2350d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2360d09e41aSPaolo Bonzini #define H_RH_PARM -18 2370d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2380d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2390d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2400d09e41aSPaolo Bonzini #define H_RT_PARM -22 2410d09e41aSPaolo Bonzini #define H_ST_PARM -23 2420d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 2430d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 2440d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 2450d09e41aSPaolo Bonzini #define H_MEM_PARM -28 2460d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 2470d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 2480d09e41aSPaolo Bonzini #define H_PORT_PARM -31 2490d09e41aSPaolo Bonzini #define H_MCG_PARM -32 2500d09e41aSPaolo Bonzini #define H_VL_PARM -33 2510d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 2520d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 2530d09e41aSPaolo Bonzini 2540d09e41aSPaolo Bonzini #define H_MASK_PARM -37 2550d09e41aSPaolo Bonzini #define H_MCG_FULL -38 2560d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 2570d09e41aSPaolo Bonzini #define H_P_COUNTER -40 2580d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 2590d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 2600d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 2610d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 2620d09e41aSPaolo Bonzini #define H_R_STATE -45 2630d09e41aSPaolo Bonzini #define H_RESCINDEND -46 26442561bf2SAnton Blanchard #define H_P2 -55 26542561bf2SAnton Blanchard #define H_P3 -56 26642561bf2SAnton Blanchard #define H_P4 -57 26742561bf2SAnton Blanchard #define H_P5 -58 26842561bf2SAnton Blanchard #define H_P6 -59 26942561bf2SAnton Blanchard #define H_P7 -60 27042561bf2SAnton Blanchard #define H_P8 -61 27142561bf2SAnton Blanchard #define H_P9 -62 27242561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 2730d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 2740d09e41aSPaolo Bonzini 2750d09e41aSPaolo Bonzini 2760d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 2770d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 2780d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 2790d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 2800d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 2810d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 2820d09e41aSPaolo Bonzini * way to check for the long_busy return codes 2830d09e41aSPaolo Bonzini */ 2840d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 2850d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 2860d09e41aSPaolo Bonzini 2870d09e41aSPaolo Bonzini /* Flags */ 2880d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 2890d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 2900d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 2910d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 2920d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 2930d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 2940d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 2950d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 2960d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 2970d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 2980d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 2990d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3000d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3010d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3020d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3030d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3040d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3050d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3060d09e41aSPaolo Bonzini 307a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 308a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 309a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 310a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 311a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 312a46622fdSAlexey Kardashevskiy 313a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 31442561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 31542561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 31642561bf2SAnton Blanchard 3170d09e41aSPaolo Bonzini /* VASI States */ 3180d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3190d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3200d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3210d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3220d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3230d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3240d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3250d09e41aSPaolo Bonzini 3260d09e41aSPaolo Bonzini /* DABRX flags */ 3270d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3280d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3290d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3300d09e41aSPaolo Bonzini 3318acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3328acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3338acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3348acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3358acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3368acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3378acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3388acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 339c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 3408acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 3418acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 3428acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 3438acc2ae5SSuraj Jitindar Singh 3440d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 3450d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 3460d09e41aSPaolo Bonzini 3470d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 3480d09e41aSPaolo Bonzini #define H_REMOVE 0x04 3490d09e41aSPaolo Bonzini #define H_ENTER 0x08 3500d09e41aSPaolo Bonzini #define H_READ 0x0c 3510d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 3520d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 3530d09e41aSPaolo Bonzini #define H_PROTECT 0x18 3540d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 3550d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 3560d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 3570d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 3580d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 3590d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 3600d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 3610d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 3620d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 3630d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 3640d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 3650d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 3660d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 3670d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 3680d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 3690d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 3700d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 3710d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 3720d09e41aSPaolo Bonzini #define H_EOI 0x64 3730d09e41aSPaolo Bonzini #define H_CPPR 0x68 3740d09e41aSPaolo Bonzini #define H_IPI 0x6c 3750d09e41aSPaolo Bonzini #define H_IPOLL 0x70 3760d09e41aSPaolo Bonzini #define H_XIRR 0x74 3770d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 3780d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 3790d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 3800d09e41aSPaolo Bonzini #define H_CEDE 0xE0 3810d09e41aSPaolo Bonzini #define H_CONFER 0xE4 3820d09e41aSPaolo Bonzini #define H_PROD 0xE8 3830d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 3840d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 3850d09e41aSPaolo Bonzini #define H_PURR 0xF4 3860d09e41aSPaolo Bonzini #define H_PIC 0xF8 3870d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 3880d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 3890d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 3900d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 3910d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 3920d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 3930d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 3940d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 3950d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 3960d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 3970d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 3980d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 3990d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4000d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4010d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4020d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4030d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4040d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4050d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4060d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4070d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4080d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4090d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4100d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4110d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4120d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4130d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4140d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4150d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4160d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4170d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4180d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4190d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4200d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4210d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4220d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4230d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4240d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4250d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4260d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4270d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4280d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4290d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4300d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 431c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4320d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4330d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4340d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4350d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4360d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4370d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4380d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4390d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 4400d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 4410d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 4420d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 4430d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 4440d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 4450d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 4460d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 4470d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 4480d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 4490d09e41aSPaolo Bonzini #define H_JOIN 0x298 4500d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 4510d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 4520d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 4530d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 4540d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 455c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 4565d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 4574d9392beSThomas Huth #define H_RANDOM 0x300 45842561bf2SAnton Blanchard #define H_SET_MODE 0x31C 45930f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 46030f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 461d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 462d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 463d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 4641c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 46523bcd5ebSCédric Le Goater 46623bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 46723bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 46823bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 46923bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 47023bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 47123bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 47223bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 47323bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 47423bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 47523bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 47623bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 47723bcd5ebSCédric Le Goater 47823bcd5ebSCédric Le Goater #define MAX_HCALL_OPCODE H_INT_RESET 4790d09e41aSPaolo Bonzini 4800d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 4810d09e41aSPaolo Bonzini * as well. 4820d09e41aSPaolo Bonzini * 4830d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 484498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 485498cd995SGreg Kurz * for "platform-specific" hcalls. 4860d09e41aSPaolo Bonzini */ 4870d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 4880d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 4890d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 4902a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 4912a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 492fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 493fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 4940d09e41aSPaolo Bonzini 4952a6593cbSAlexey Kardashevskiy typedef struct sPAPRDeviceTreeUpdateHeader { 4962a6593cbSAlexey Kardashevskiy uint32_t version_id; 4972a6593cbSAlexey Kardashevskiy } sPAPRDeviceTreeUpdateHeader; 4982a6593cbSAlexey Kardashevskiy 4990d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 500aaf87c66SThomas Huth do { \ 501aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 502aaf87c66SThomas Huth } while (0) 5030d09e41aSPaolo Bonzini 50428e02042SDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 5050d09e41aSPaolo Bonzini target_ulong opcode, 5060d09e41aSPaolo Bonzini target_ulong *args); 5070d09e41aSPaolo Bonzini 5080d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5090d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5100d09e41aSPaolo Bonzini target_ulong *args); 5110d09e41aSPaolo Bonzini 512ee954280SGavin Shan /* ibm,set-eeh-option */ 513ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 514ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 515ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 516ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 517ee954280SGavin Shan 518ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 519ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 520ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 521ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 522ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 523ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 524ee954280SGavin Shan 525ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 526ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 527ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 528ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 529ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 530ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 531ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 532ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 533ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 534ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 535ee954280SGavin Shan 536ee954280SGavin Shan /* ibm,set-slot-reset */ 537ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 538ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 539ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 540ee954280SGavin Shan 541ee954280SGavin Shan /* ibm,slot-error-detail */ 542ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 543ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 544ee954280SGavin Shan 545a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 546a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 547a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 548a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 549a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 550a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 5513ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 5529d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 5533ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 554c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 555a64d325dSAlexey Kardashevskiy 556ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 557ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 558ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 559ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 560ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 561ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 562ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 563ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 564ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 565ae4de14cSAlexey Kardashevskiy 5663a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 5673a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 5683a3b8502SAlexey Kardashevskiy 5693a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 5703a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 5713a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 5723a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 5733a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 5743a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 5753a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 5763a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 5773a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 5783a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 5793a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 5803a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 5813a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 5823a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 5833a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 5843a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 5853a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 5863a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 5873a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 5883a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 5893a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 5903a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 5913a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 5923a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 5933a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 5943a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 5953a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 5963a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 5973a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 5983a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 5993a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6003a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 601ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 602ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 603ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 604ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 605ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 606ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 607ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 608ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 609ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 610ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 6113a3b8502SAlexey Kardashevskiy 612ae4de14cSAlexey Kardashevskiy #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 6133a3b8502SAlexey Kardashevskiy 6143052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 6153b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 6163052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 617b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 6183052d951SSam bobroff 6198c8639dfSMike Day /* RTAS indicator/sensor types 6208c8639dfSMike Day * 6218c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 6228c8639dfSMike Day * 6238c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 6248c8639dfSMike Day */ 6258c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 6268c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 6278c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 6288c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 6298c8639dfSMike Day 6303052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 6313052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 6323052d951SSam bobroff */ 6333052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 6343052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 6353052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 6363052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 6373052d951SSam bobroff 6384fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 6394fe822e0SAlexey Kardashevskiy { 6404fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 6414fe822e0SAlexey Kardashevskiy } 6424fe822e0SAlexey Kardashevskiy 6430d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 6440d09e41aSPaolo Bonzini { 645fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 6460d09e41aSPaolo Bonzini } 6470d09e41aSPaolo Bonzini 648a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 649a14aa92bSGavin Shan { 650a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 651a14aa92bSGavin Shan } 652a14aa92bSGavin Shan 6530d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 6540d09e41aSPaolo Bonzini { 655ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 6560d09e41aSPaolo Bonzini } 6570d09e41aSPaolo Bonzini 65828e02042SDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 659210b580bSAnthony Liguori uint32_t token, 6600d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 6610d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 6623a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 66328e02042SDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 6640d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 6650d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 6663f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 6672cac78c1SDavid Gibson void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 6680d09e41aSPaolo Bonzini 6690d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 6700d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 6710d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 6720d09e41aSPaolo Bonzini 6730d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 6744290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 675c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 676c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 677d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 678c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 6790d09e41aSPaolo Bonzini 6800d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 6810d09e41aSPaolo Bonzini 68279853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 68379853e18STyrel Datwyler 684bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 685bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 686bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 687bb2d8ab6SGreg Kurz */ 6885c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 689bb2d8ab6SGreg Kurz { 690bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 691bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 692bb2d8ab6SGreg Kurz } 693bb2d8ab6SGreg Kurz 6942b7dc949SPaolo Bonzini typedef struct sPAPRTCETable sPAPRTCETable; 6950d09e41aSPaolo Bonzini 696a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 697a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 698a83000f5SAnthony Liguori OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 699a83000f5SAnthony Liguori 7001221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 7011221a474SAlexey Kardashevskiy #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 7021221a474SAlexey Kardashevskiy OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 7031221a474SAlexey Kardashevskiy 704a83000f5SAnthony Liguori struct sPAPRTCETable { 705a83000f5SAnthony Liguori DeviceState parent; 706a83000f5SAnthony Liguori uint32_t liobn; 707a83000f5SAnthony Liguori uint32_t nb_table; 7081b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 709650f33adSAlexey Kardashevskiy uint32_t page_shift; 710a83000f5SAnthony Liguori uint64_t *table; 711a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 712a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 713a83000f5SAnthony Liguori bool bypass; 7146a81dd17SDavid Gibson bool need_vfio; 715a83000f5SAnthony Liguori int fd; 7163df9d748SAlexey Kardashevskiy MemoryRegion root; 7173df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 718ee9a569aSAlexey Kardashevskiy struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 719a83000f5SAnthony Liguori QLIST_ENTRY(sPAPRTCETable) list; 720a83000f5SAnthony Liguori }; 721a83000f5SAnthony Liguori 722f9ce8e0aSThomas Huth sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 72331fe14d1SNathan Fontenot 7245341258eSDavid Gibson struct sPAPREventLogEntry { 725fd38804bSDaniel Henrique Barboza uint32_t summary; 726fd38804bSDaniel Henrique Barboza uint32_t extended_length; 727fd38804bSDaniel Henrique Barboza void *extended_log; 72831fe14d1SNathan Fontenot QTAILQ_ENTRY(sPAPREventLogEntry) next; 72931fe14d1SNathan Fontenot }; 73031fe14d1SNathan Fontenot 73128e02042SDavid Gibson void spapr_events_init(sPAPRMachineState *sm); 732ffbb1705SMichael Roth void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 73328e02042SDavid Gibson int spapr_h_cas_compose_response(sPAPRMachineState *sm, 73403d196b7SBharata B Rao target_ulong addr, target_ulong size, 7356787d27bSMichael Roth sPAPROptionVector *ov5_updates); 736b4db5413SSuraj Jitindar Singh void close_htab_fd(sPAPRMachineState *spapr); 737b4db5413SSuraj Jitindar Singh void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 73806ec79e8SBharata B Rao void spapr_free_hpt(sPAPRMachineState *spapr); 739df7625d4SAlexey Kardashevskiy sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 740df7625d4SAlexey Kardashevskiy void spapr_tce_table_enable(sPAPRTCETable *tcet, 741df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 742df7625d4SAlexey Kardashevskiy uint32_t nb_table); 743a26fdf39SAlexey Kardashevskiy void spapr_tce_table_disable(sPAPRTCETable *tcet); 744c10325d6SDavid Gibson void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 745c10325d6SDavid Gibson 746a84bb436SPaolo Bonzini MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 7470d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 7480d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 7490d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 7502b7dc949SPaolo Bonzini sPAPRTCETable *tcet); 751eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 7527a36ae7aSBharata B Rao void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 7537a36ae7aSBharata B Rao void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 7547a36ae7aSBharata B Rao void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 7557a36ae7aSBharata B Rao uint32_t count); 7567a36ae7aSBharata B Rao void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 7577a36ae7aSBharata B Rao uint32_t count); 758afdbd403SBharata B Rao void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 759afdbd403SBharata B Rao uint32_t count, uint32_t index); 760afdbd403SBharata B Rao void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 761afdbd403SBharata B Rao uint32_t count, uint32_t index); 7620b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 7632772cf6bSDavid Gibson void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 7642772cf6bSDavid Gibson Error **errp); 76556258174SDaniel Henrique Barboza void spapr_clear_pending_events(sPAPRMachineState *spapr); 7661a518e76SCédric Le Goater int spapr_max_server_number(sPAPRMachineState *spapr); 76728df36a1SDavid Gibson 76862d38c9bSGreg Kurz /* DRC callbacks. */ 76931834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 770345b12b9SGreg Kurz int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 771345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 77231834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 77362d38c9bSGreg Kurz int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 77462d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 775*bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 776*bb2bdd81SGreg Kurz int spapr_phb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 777*bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 77831834723SDaniel Henrique Barboza 779147ff807SCédric Le Goater void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 780147ff807SCédric Le Goater int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 78128df36a1SDavid Gibson 782147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 7830d09e41aSPaolo Bonzini 784db4ef288SBharata B Rao #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 785db4ef288SBharata B Rao 7864a1c9cf0SBharata B Rao /* 7874a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 7884a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 7894a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 7904a1c9cf0SBharata B Rao */ 7914a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 7924a1c9cf0SBharata B Rao 793ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 794ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 7954a1c9cf0SBharata B Rao 79603d196b7SBharata B Rao /* 79703d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 79803d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 79903d196b7SBharata B Rao */ 80003d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 80103d196b7SBharata B Rao 80203d196b7SBharata B Rao /* 803d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 804d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 80503d196b7SBharata B Rao */ 80603d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 807d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 808d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 80903d196b7SBharata B Rao 8101c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 8111c7ad77eSNicholas Piggin 8120b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 8130b0b8310SDavid Gibson 81414bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 815648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 8162e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 8172e886fb3SSam Bobroff 8184e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 8194e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 8204e5fe368SSuraj Jitindar Singh 82133face6bSDavid Gibson /* 82233face6bSDavid Gibson * Handling of optional capabilities 82333face6bSDavid Gibson */ 8244e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 8254e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 8264e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 8278f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 82809114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 8294be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 830b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 831be85537dSDavid Gibson 8324e5fe368SSuraj Jitindar Singh static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 83333face6bSDavid Gibson { 8344e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 83533face6bSDavid Gibson } 83633face6bSDavid Gibson 8379f6edd06SDavid Gibson void spapr_caps_init(sPAPRMachineState *spapr); 8389f6edd06SDavid Gibson void spapr_caps_apply(sPAPRMachineState *spapr); 839e2e4f641SDavid Gibson void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); 84033face6bSDavid Gibson void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 841be85537dSDavid Gibson int spapr_caps_post_migration(sPAPRMachineState *spapr); 84233face6bSDavid Gibson 843123eec65SDavid Gibson void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, 844123eec65SDavid Gibson Error **errp); 845db592b5bSCédric Le Goater /* 846db592b5bSCédric Le Goater * XIVE definitions 847db592b5bSCédric Le Goater */ 848db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 849db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 850db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 851123eec65SDavid Gibson 85200fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 8532a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 854