12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 120d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 130fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 140d09e41aSPaolo Bonzini 15ce2918cbSDavid Gibson struct SpaprVioBus; 16ce2918cbSDavid Gibson struct SpaprPhbState; 17ce2918cbSDavid Gibson struct SpaprNvram; 180d8d6a24SThomas Huth 19ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 21ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 220d09e41aSPaolo Bonzini 234be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 241b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 254be21d56SDavid Gibson 26afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 27afd10a0fSBharata B Rao 28147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 29147ff807SCédric Le Goater 30147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 31ce2918cbSDavid Gibson OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32147ff807SCédric Le Goater 33ce2918cbSDavid Gibson typedef struct SpaprRtcState SpaprRtcState; 34ce2918cbSDavid Gibson struct SpaprRtcState { 35147ff807SCédric Le Goater /*< private >*/ 36147ff807SCédric Le Goater DeviceState parent_obj; 37147ff807SCédric Le Goater int64_t ns_offset; 38147ff807SCédric Le Goater }; 39147ff807SCédric Le Goater 40ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 41ce2918cbSDavid Gibson typedef struct SpaprMachineClass SpaprMachineClass; 4228e02042SDavid Gibson 4328e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 44*82d1e74fSEduardo Habkost typedef struct SpaprMachineState SpaprMachineState; 4528e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 46ce2918cbSDavid Gibson OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 47183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 48ce2918cbSDavid Gibson OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 49183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 50ce2918cbSDavid Gibson OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 51183930c0SDavid Gibson 5230f4b05bSDavid Gibson typedef enum { 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5430f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5530f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5630f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 57ce2918cbSDavid Gibson } SpaprResizeHpt; 5830f4b05bSDavid Gibson 59183930c0SDavid Gibson /** 6033face6bSDavid Gibson * Capabilities 6133face6bSDavid Gibson */ 6233face6bSDavid Gibson 63ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 644e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6529386642SDavid Gibson /* Vector Scalar Extensions */ 664e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 672d1fb9bcSDavid Gibson /* Decimal Floating Point */ 684e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 698f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 708f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 7109114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 7209114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 734be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 744be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 752309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 762309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 77b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 78b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 79c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 80c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 818ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 828ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 838af7e1feSNicholas Piggin /* Implements PAPR FWNMI option */ 848af7e1feSNicholas Piggin #define SPAPR_CAP_FWNMI 0x0A 854e5fe368SSuraj Jitindar Singh /* Num Caps */ 868af7e1feSNicholas Piggin #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1) 874e5fe368SSuraj Jitindar Singh 884e5fe368SSuraj Jitindar Singh /* 894e5fe368SSuraj Jitindar Singh * Capability Values 904e5fe368SSuraj Jitindar Singh */ 914e5fe368SSuraj Jitindar Singh /* Bool Caps */ 924e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 934e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 94399b2896SSuraj Jitindar Singh 95c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 96399b2896SSuraj Jitindar Singh 97399b2896SSuraj Jitindar Singh /* Generic */ 986898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 996898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 1006898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 101399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 102c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 103c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 104399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1052d1fb9bcSDavid Gibson 10691067db1SAlexey Kardashevskiy #define FDT_MAX_SIZE 0x100000 10791067db1SAlexey Kardashevskiy 108ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 109ce2918cbSDavid Gibson struct SpaprCapabilities { 1104e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 11133face6bSDavid Gibson }; 11233face6bSDavid Gibson 11333face6bSDavid Gibson /** 114ce2918cbSDavid Gibson * SpaprMachineClass: 115183930c0SDavid Gibson */ 116ce2918cbSDavid Gibson struct SpaprMachineClass { 117183930c0SDavid Gibson /*< private >*/ 118183930c0SDavid Gibson MachineClass parent_class; 119183930c0SDavid Gibson 120183930c0SDavid Gibson /*< public >*/ 121224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 122962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 123fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 12457040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 12546f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 12682cffa2eSCédric Le Goater bool legacy_irq_allocation; 12754255c1fSDavid Gibson uint32_t nr_xirqs; 1280a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1293725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1306c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 13129cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 1321052ab67SDavid Gibson hwaddr rma_limit; /* clamp the RMA to this size */ 133a6030d7eSReza Arbab bool pre_5_1_assoc_refpoints; 13482cffa2eSCédric Le Goater 135ce2918cbSDavid Gibson void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 136daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 137daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 138ec132efaSAlexey Kardashevskiy unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 139ec132efaSAlexey Kardashevskiy hwaddr *nv2atsd, Error **errp); 140ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 141ce2918cbSDavid Gibson SpaprCapabilities default_caps; 142ce2918cbSDavid Gibson SpaprIrq *irq; 143183930c0SDavid Gibson }; 14428e02042SDavid Gibson 14528e02042SDavid Gibson /** 146ce2918cbSDavid Gibson * SpaprMachineState: 14728e02042SDavid Gibson */ 148ce2918cbSDavid Gibson struct SpaprMachineState { 14928e02042SDavid Gibson /*< private >*/ 15028e02042SDavid Gibson MachineState parent_obj; 15128e02042SDavid Gibson 152ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 153ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 154ce2918cbSDavid Gibson struct SpaprNvram *nvram; 155ce2918cbSDavid Gibson SpaprRtcState rtc; 1560d09e41aSPaolo Bonzini 157ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1580d09e41aSPaolo Bonzini void *htab; 1594be21d56SDavid Gibson uint32_t htab_shift; 1609861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 161ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1620b0b8310SDavid Gibson 1630d09e41aSPaolo Bonzini hwaddr rma_size; 164fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 165fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 166fea35ca4SAlexey Kardashevskiy void *fdt_blob; 167a19f7fb0SDavid Gibson long kernel_size; 168a19f7fb0SDavid Gibson bool kernel_le; 16987262806SAlexey Kardashevskiy uint64_t kernel_addr; 170a19f7fb0SDavid Gibson uint32_t initrd_base; 171a19f7fb0SDavid Gibson long initrd_size; 172880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 17398a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1740d09e41aSPaolo Bonzini bool has_graphics; 175fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1760d09e41aSPaolo Bonzini 1770d09e41aSPaolo Bonzini Notifier epow_notifier; 178ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 179ffbb1705SMichael Roth bool use_hotplug_event_source; 180ce2918cbSDavid Gibson SpaprEventSource *event_sources; 1814be21d56SDavid Gibson 1827843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 183daa36379SDavid Gibson bool cas_pre_isa3_guest; 184ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 185ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1867843c0d6SDavid Gibson uint32_t max_compat_pvr; 1877843c0d6SDavid Gibson 1884be21d56SDavid Gibson /* Migration state */ 1894be21d56SDavid Gibson int htab_save_index; 1904be21d56SDavid Gibson bool htab_first_pass; 191e68cb8b4SAlexey Kardashevskiy int htab_fd; 19246503c2bSMichael Roth 1930cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1940cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1950cffce56SDavid Gibson * occurs during the unplug process. */ 196ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 1970cffce56SDavid Gibson 1988af7e1feSNicholas Piggin /* State related to FWNMI option */ 1998af7e1feSNicholas Piggin 200edfdbf9cSNicholas Piggin /* System Reset and Machine Check Notification Routine addresses 2018af7e1feSNicholas Piggin * registered by "ibm,nmi-register" RTAS call. 2029ac703acSAravinda Prasad */ 203edfdbf9cSNicholas Piggin target_ulong fwnmi_system_reset_addr; 2048af7e1feSNicholas Piggin target_ulong fwnmi_machine_check_addr; 2058af7e1feSNicholas Piggin 2068af7e1feSNicholas Piggin /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 2078af7e1feSNicholas Piggin * set to -1 if a FWNMI machine check is not in progress, else is set to 2088af7e1feSNicholas Piggin * the CPU that was delivered the machine check, and is set back to -1 2098af7e1feSNicholas Piggin * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 2108af7e1feSNicholas Piggin * to synchronize other CPUs. 2118af7e1feSNicholas Piggin */ 2128af7e1feSNicholas Piggin int fwnmi_machine_check_interlock; 2138af7e1feSNicholas Piggin QemuCond fwnmi_machine_check_interlock_cond; 2149ac703acSAravinda Prasad 21528e02042SDavid Gibson /*< public >*/ 21628e02042SDavid Gibson char *kvm_type; 21727461d69SPrasad J Pandit char *host_model; 21827461d69SPrasad J Pandit char *host_serial; 219852ad27eSCédric Le Goater 22082cffa2eSCédric Le Goater int32_t irq_map_nr; 22182cffa2eSCédric Le Goater unsigned long *irq_map; 222ce2918cbSDavid Gibson SpaprIrq *irq; 223872ff3deSCédric Le Goater qemu_irq *qirqs; 22481106dddSDavid Gibson SpaprInterruptController *active_intc; 22581106dddSDavid Gibson ICSState *ics; 22681106dddSDavid Gibson SpaprXive *xive; 22733face6bSDavid Gibson 2284e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 229ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 230ec132efaSAlexey Kardashevskiy 231ec132efaSAlexey Kardashevskiy unsigned gpu_numa_id; 2320fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 2332500fb42SAravinda Prasad 2342500fb42SAravinda Prasad Error *fwnmi_migration_blocker; 23528e02042SDavid Gibson }; 2360d09e41aSPaolo Bonzini 2370d09e41aSPaolo Bonzini #define H_SUCCESS 0 2380d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2390d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2400d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2410d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2420d09e41aSPaolo Bonzini #define H_PARTIAL 5 2430d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2440d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2450d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2460d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2470d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2480d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2490d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2500d09e41aSPaolo Bonzini is a good time to retry */ 2510d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2520d09e41aSPaolo Bonzini is a good time to retry */ 2530d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2540d09e41aSPaolo Bonzini is a good time to retry */ 2550d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2560d09e41aSPaolo Bonzini is a good time to retry */ 2570d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2580d09e41aSPaolo Bonzini is a good time to retry */ 2590d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2600d09e41aSPaolo Bonzini is a good time to retry */ 2610d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2620d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2630d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2640d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2650d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2660d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2670d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2680d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2690d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2700d09e41aSPaolo Bonzini #define H_NO_MEM -9 2710d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2720d09e41aSPaolo Bonzini #define H_PERMISSION -11 2730d09e41aSPaolo Bonzini #define H_DROPPED -12 2740d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2750d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2760d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2770d09e41aSPaolo Bonzini #define H_RESOURCE -16 2780d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2790d09e41aSPaolo Bonzini #define H_RH_PARM -18 2800d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2810d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2820d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2830d09e41aSPaolo Bonzini #define H_RT_PARM -22 2840d09e41aSPaolo Bonzini #define H_ST_PARM -23 2850d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 2860d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 2870d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 2880d09e41aSPaolo Bonzini #define H_MEM_PARM -28 2890d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 2900d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 2910d09e41aSPaolo Bonzini #define H_PORT_PARM -31 2920d09e41aSPaolo Bonzini #define H_MCG_PARM -32 2930d09e41aSPaolo Bonzini #define H_VL_PARM -33 2940d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 2950d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 2960d09e41aSPaolo Bonzini 2970d09e41aSPaolo Bonzini #define H_MASK_PARM -37 2980d09e41aSPaolo Bonzini #define H_MCG_FULL -38 2990d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 3000d09e41aSPaolo Bonzini #define H_P_COUNTER -40 3010d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 3020d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 3030d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 3040d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 3050d09e41aSPaolo Bonzini #define H_R_STATE -45 3060d09e41aSPaolo Bonzini #define H_RESCINDEND -46 30742561bf2SAnton Blanchard #define H_P2 -55 30842561bf2SAnton Blanchard #define H_P3 -56 30942561bf2SAnton Blanchard #define H_P4 -57 31042561bf2SAnton Blanchard #define H_P5 -58 31142561bf2SAnton Blanchard #define H_P6 -59 31242561bf2SAnton Blanchard #define H_P7 -60 31342561bf2SAnton Blanchard #define H_P8 -61 31442561bf2SAnton Blanchard #define H_P9 -62 315b5fca656SShivaprasad G Bhat #define H_OVERLAP -68 31642561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 3170d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 3180d09e41aSPaolo Bonzini 3190d09e41aSPaolo Bonzini 3200d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 3210d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 3220d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 3230d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 3240d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 3250d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3260d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3270d09e41aSPaolo Bonzini */ 3280d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3290d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3300d09e41aSPaolo Bonzini 3310d09e41aSPaolo Bonzini /* Flags */ 3320d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3330d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3340d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3350d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3360d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3370d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3380d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3390d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3400d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3410d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3420d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3430d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3440d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3450d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3460d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3470d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3480d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3490d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3500d09e41aSPaolo Bonzini 351a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 352a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 353a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 354a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 355a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 356a46622fdSAlexey Kardashevskiy 357a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 35842561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 35942561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 36042561bf2SAnton Blanchard 3610d09e41aSPaolo Bonzini /* VASI States */ 3620d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3630d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3640d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3650d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3660d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3670d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3680d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3690d09e41aSPaolo Bonzini 3700d09e41aSPaolo Bonzini /* DABRX flags */ 3710d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3720d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3730d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3740d09e41aSPaolo Bonzini 3758acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3768acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3778acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3788acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3798acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3808acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3818acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3828acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 383c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 384399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 3858acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 3868acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 3878acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 388399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 3898acc2ae5SSuraj Jitindar Singh 3900d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 3910d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 3920d09e41aSPaolo Bonzini 3930d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 3940d09e41aSPaolo Bonzini #define H_REMOVE 0x04 3950d09e41aSPaolo Bonzini #define H_ENTER 0x08 3960d09e41aSPaolo Bonzini #define H_READ 0x0c 3970d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 3980d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 3990d09e41aSPaolo Bonzini #define H_PROTECT 0x18 4000d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 4010d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 4020d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 4030d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 4040d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 4050d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 4060d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 4070d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 4080d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 4090d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 4100d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 4110d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 4120d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 4130d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 4140d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 4150d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 4160d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 4170d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 4180d09e41aSPaolo Bonzini #define H_EOI 0x64 4190d09e41aSPaolo Bonzini #define H_CPPR 0x68 4200d09e41aSPaolo Bonzini #define H_IPI 0x6c 4210d09e41aSPaolo Bonzini #define H_IPOLL 0x70 4220d09e41aSPaolo Bonzini #define H_XIRR 0x74 4230d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 4240d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 4250d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4260d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4270d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4280d09e41aSPaolo Bonzini #define H_PROD 0xE8 4290d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4300d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4310d09e41aSPaolo Bonzini #define H_PURR 0xF4 4320d09e41aSPaolo Bonzini #define H_PIC 0xF8 4330d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4340d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4350d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4360d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4370d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4380d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4390d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4400d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4410d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4420d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4430d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4440d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4450d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4460d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4470d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4480d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4490d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4500d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4510d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4520d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4530d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4540d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4550d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4560d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4570d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4580d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4590d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4600d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4610d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4620d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4630d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4640d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4650d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4660d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4670d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4680d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4690d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4700d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4710d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4720d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4730d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4740d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4750d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4760d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 477c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4780d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4790d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4800d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4810d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4820d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4830d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4840d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4850d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 4860d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 4870d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 4880d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 4890d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 4900d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 4910d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 4920d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 4930d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 4940d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 4950d09e41aSPaolo Bonzini #define H_JOIN 0x298 4960d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 4970d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 4980d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 4990d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 5000d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 501c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 5025d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 5034d9392beSThomas Huth #define H_RANDOM 0x300 50442561bf2SAnton Blanchard #define H_SET_MODE 0x31C 50530f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 50630f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 507d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 508d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 509d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 5101c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 51123bcd5ebSCédric Le Goater 51223bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 51323bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 51423bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 51523bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 51623bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 51723bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 51823bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 51923bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 52023bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 52123bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 52223bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 523b5fca656SShivaprasad G Bhat #define H_SCM_READ_METADATA 0x3E4 524b5fca656SShivaprasad G Bhat #define H_SCM_WRITE_METADATA 0x3E8 525b5fca656SShivaprasad G Bhat #define H_SCM_BIND_MEM 0x3EC 526b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_MEM 0x3F0 527b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_ALL 0x3FC 52823bcd5ebSCédric Le Goater 529b5fca656SShivaprasad G Bhat #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 5300d09e41aSPaolo Bonzini 5310d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5320d09e41aSPaolo Bonzini * as well. 5330d09e41aSPaolo Bonzini * 5340d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 535498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 536498cd995SGreg Kurz * for "platform-specific" hcalls. 5370d09e41aSPaolo Bonzini */ 5380d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5390d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5400d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5412a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5422a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 543fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 544fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 5450d09e41aSPaolo Bonzini 5460fb6bd07SMichael Roth /* 5470fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 5480fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 5490fb6bd07SMichael Roth */ 5500fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 5510fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 5520fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 5530fb6bd07SMichael Roth 5540fb6bd07SMichael Roth 555ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 5562a6593cbSAlexey Kardashevskiy uint32_t version_id; 557ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 5582a6593cbSAlexey Kardashevskiy 5590d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 560aaf87c66SThomas Huth do { \ 561aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 562aaf87c66SThomas Huth } while (0) 5630d09e41aSPaolo Bonzini 564ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 5650d09e41aSPaolo Bonzini target_ulong opcode, 5660d09e41aSPaolo Bonzini target_ulong *args); 5670d09e41aSPaolo Bonzini 5680d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5690d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5700d09e41aSPaolo Bonzini target_ulong *args); 5710d09e41aSPaolo Bonzini 57291067db1SAlexey Kardashevskiy target_ulong do_client_architecture_support(PowerPCCPU *cpu, 57391067db1SAlexey Kardashevskiy SpaprMachineState *spapr, 57491067db1SAlexey Kardashevskiy target_ulong addr, 57591067db1SAlexey Kardashevskiy target_ulong fdt_bufsize); 57691067db1SAlexey Kardashevskiy 57703ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 57803ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 57903ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 58003ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 58103ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 58203ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 58303ef074cSNicholas Piggin 584ee954280SGavin Shan /* ibm,set-eeh-option */ 585ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 586ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 587ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 588ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 589ee954280SGavin Shan 590ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 591ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 592ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 593ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 594ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 595ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 596ee954280SGavin Shan 597ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 598ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 599ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 600ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 601ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 602ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 603ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 604ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 605ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 606ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 607ee954280SGavin Shan 608ee954280SGavin Shan /* ibm,set-slot-reset */ 609ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 610ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 611ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 612ee954280SGavin Shan 613ee954280SGavin Shan /* ibm,slot-error-detail */ 614ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 615ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 616ee954280SGavin Shan 617a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 618a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 619a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 620a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 621a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 622a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 6233ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 6249d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 6253ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 626c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 627a64d325dSAlexey Kardashevskiy 628ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 629ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 630ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 631ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 632ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 633ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 634ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 635ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 636ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 637ae4de14cSAlexey Kardashevskiy 6383a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 6393a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 6403a3b8502SAlexey Kardashevskiy 6413a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 6423a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 6433a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 6443a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 6453a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 6463a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 6473a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 6483a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 6493a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 6503a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 6513a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 6523a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 6533a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 6543a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 6553a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 6563a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 6573a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 6583a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 6593a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 6603a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 6613a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 6623a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 6633a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 6643a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 6653a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 6663a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 6673a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 6683a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 6693a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 6703a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 6713a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6723a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 673ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 674ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 675ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 676ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 677ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 678ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 679ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 680ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 681ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 682ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 68393eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 684f03496bcSAravinda Prasad #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 685f03496bcSAravinda Prasad #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 6863a3b8502SAlexey Kardashevskiy 687f03496bcSAravinda Prasad #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 6883a3b8502SAlexey Kardashevskiy 6893052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 6903b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 6913052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 692b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 6933052d951SSam bobroff 6948c8639dfSMike Day /* RTAS indicator/sensor types 6958c8639dfSMike Day * 6968c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 6978c8639dfSMike Day * 6988c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 6998c8639dfSMike Day */ 7008c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 7018c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 7028c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 7038c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 7048c8639dfSMike Day 7053052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 7063052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 7073052d951SSam bobroff */ 7083052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 7093052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 7103052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 7113052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 7123052d951SSam bobroff 7134fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 7144fe822e0SAlexey Kardashevskiy { 7154fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 7164fe822e0SAlexey Kardashevskiy } 7174fe822e0SAlexey Kardashevskiy 7180d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 7190d09e41aSPaolo Bonzini { 720fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 7210d09e41aSPaolo Bonzini } 7220d09e41aSPaolo Bonzini 723a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 724a14aa92bSGavin Shan { 725a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 726a14aa92bSGavin Shan } 727a14aa92bSGavin Shan 7280d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 7290d09e41aSPaolo Bonzini { 730ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 7310d09e41aSPaolo Bonzini } 7320d09e41aSPaolo Bonzini 733ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 734210b580bSAnthony Liguori uint32_t token, 7350d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 7360d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7373a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 738ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 7390d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 7400d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7413f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 742ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 7430d09e41aSPaolo Bonzini 7440d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 7450d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 7460d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 7470d09e41aSPaolo Bonzini 7480d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 7494290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 750c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 751c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 752d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 753c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 7540d09e41aSPaolo Bonzini 7554dba8722SAlexey Kardashevskiy #define RTAS_SIZE 2048 7560d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 7570d09e41aSPaolo Bonzini 75881fe70e4SAravinda Prasad /* Offset from rtas-base where error log is placed */ 75981fe70e4SAravinda Prasad #define RTAS_ERROR_LOG_OFFSET 0x30 76081fe70e4SAravinda Prasad 76179853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 76279853e18STyrel Datwyler 763bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 764bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 765bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 766bb2d8ab6SGreg Kurz */ 7675c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 768bb2d8ab6SGreg Kurz { 769bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 770bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 771bb2d8ab6SGreg Kurz } 772bb2d8ab6SGreg Kurz 773ce2918cbSDavid Gibson typedef struct SpaprTceTable SpaprTceTable; 7740d09e41aSPaolo Bonzini 775a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 776a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 777ce2918cbSDavid Gibson OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 778a83000f5SAnthony Liguori 7791221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 7801221a474SAlexey Kardashevskiy #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 7811221a474SAlexey Kardashevskiy OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 7821221a474SAlexey Kardashevskiy 783ce2918cbSDavid Gibson struct SpaprTceTable { 784a83000f5SAnthony Liguori DeviceState parent; 785a83000f5SAnthony Liguori uint32_t liobn; 786a83000f5SAnthony Liguori uint32_t nb_table; 7871b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 788650f33adSAlexey Kardashevskiy uint32_t page_shift; 789a83000f5SAnthony Liguori uint64_t *table; 790a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 791a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 792a83000f5SAnthony Liguori bool bypass; 7936a81dd17SDavid Gibson bool need_vfio; 7945f366667SAlexey Kardashevskiy bool skipping_replay; 795a83000f5SAnthony Liguori int fd; 7963df9d748SAlexey Kardashevskiy MemoryRegion root; 7973df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 798ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 799ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 800a83000f5SAnthony Liguori }; 801a83000f5SAnthony Liguori 802ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 80331fe14d1SNathan Fontenot 804ce2918cbSDavid Gibson struct SpaprEventLogEntry { 805fd38804bSDaniel Henrique Barboza uint32_t summary; 806fd38804bSDaniel Henrique Barboza uint32_t extended_length; 807fd38804bSDaniel Henrique Barboza void *extended_log; 808ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 80931fe14d1SNathan Fontenot }; 81031fe14d1SNathan Fontenot 8110c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 812ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 813ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 814ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 8158897ea5aSDavid Gibson void spapr_setup_hpt(SpaprMachineState *spapr); 816ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 817ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 818ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 819df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 820df7625d4SAlexey Kardashevskiy uint32_t nb_table); 821ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 822ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 823c10325d6SDavid Gibson 824ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 8250d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 8260d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 8270d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 828ce2918cbSDavid Gibson SpaprTceTable *tcet); 829eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 830ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 831ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 832ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 8337a36ae7aSBharata B Rao uint32_t count); 834ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 8357a36ae7aSBharata B Rao uint32_t count); 836ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 837afdbd403SBharata B Rao uint32_t count, uint32_t index); 838ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 839afdbd403SBharata B Rao uint32_t count, uint32_t index); 8400b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 841ce2918cbSDavid Gibson void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 8422772cf6bSDavid Gibson Error **errp); 843ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 844ad334d89SGreg Kurz void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 845ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 846a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 847a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 84881fe70e4SAravinda Prasad void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 84928df36a1SDavid Gibson 85062d38c9bSGreg Kurz /* DRC callbacks. */ 85131834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 852ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 853345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 85431834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 855ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 85662d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 857bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 858ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 859bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 86031834723SDaniel Henrique Barboza 861ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 862ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 86328df36a1SDavid Gibson 864147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 8650d09e41aSPaolo Bonzini 866e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 867db4ef288SBharata B Rao 8684a1c9cf0SBharata B Rao /* 8694a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 8704a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 8714a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 8724a1c9cf0SBharata B Rao */ 8734a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 8744a1c9cf0SBharata B Rao 875ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 876ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 8774a1c9cf0SBharata B Rao 87803d196b7SBharata B Rao /* 87903d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 88003d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 88103d196b7SBharata B Rao */ 88203d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 88303d196b7SBharata B Rao 88403d196b7SBharata B Rao /* 885d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 886d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 88703d196b7SBharata B Rao */ 88803d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 889d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 890d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 8910911a60cSLeonardo Bras #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 89203d196b7SBharata B Rao 8931c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 8941c7ad77eSNicholas Piggin 8950b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 8960b0b8310SDavid Gibson 89714bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 898648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 8992e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 9002e886fb3SSam Bobroff 9014e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 9024e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 9034e5fe368SSuraj Jitindar Singh 90433face6bSDavid Gibson /* 90533face6bSDavid Gibson * Handling of optional capabilities 90633face6bSDavid Gibson */ 9074e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 9084e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 9094e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 9108f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 91109114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 9124be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 91364d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 914b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 915c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 9168ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 9179d953ce4SAravinda Prasad extern const VMStateDescription vmstate_spapr_cap_fwnmi; 918be85537dSDavid Gibson 919ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 92033face6bSDavid Gibson { 9214e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 92233face6bSDavid Gibson } 92333face6bSDavid Gibson 924ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 925ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 926ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 92740c2281cSMarkus Armbruster void spapr_caps_add_properties(SpaprMachineClass *smc); 928ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 92933face6bSDavid Gibson 930ce2918cbSDavid Gibson void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 931123eec65SDavid Gibson Error **errp); 932db592b5bSCédric Le Goater /* 933db592b5bSCédric Le Goater * XIVE definitions 934db592b5bSCédric Le Goater */ 935db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 936db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 937db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 938123eec65SDavid Gibson 93900fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 94081fe70e4SAravinda Prasad hwaddr spapr_get_rtas_addr(void); 9412a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 942