12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11db1015e9SEduardo Habkost #include "qom/object.h" 12ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 130d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 140fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 150d09e41aSPaolo Bonzini 16ce2918cbSDavid Gibson struct SpaprVioBus; 17ce2918cbSDavid Gibson struct SpaprPhbState; 18ce2918cbSDavid Gibson struct SpaprNvram; 190d8d6a24SThomas Huth 20ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 22ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 230d09e41aSPaolo Bonzini 244be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 251b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 264be21d56SDavid Gibson 27afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 28afd10a0fSBharata B Rao 29147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 30147ff807SCédric Le Goater 31db1015e9SEduardo Habkost typedef struct SpaprRtcState SpaprRtcState; 32*8110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(SpaprRtcState, SPAPR_RTC, 33*8110fa1dSEduardo Habkost TYPE_SPAPR_RTC) 34147ff807SCédric Le Goater 35ce2918cbSDavid Gibson struct SpaprRtcState { 36147ff807SCédric Le Goater /*< private >*/ 37147ff807SCédric Le Goater DeviceState parent_obj; 38147ff807SCédric Le Goater int64_t ns_offset; 39147ff807SCédric Le Goater }; 40147ff807SCédric Le Goater 41ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 42ce2918cbSDavid Gibson typedef struct SpaprMachineClass SpaprMachineClass; 4328e02042SDavid Gibson 4428e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 4582d1e74fSEduardo Habkost typedef struct SpaprMachineState SpaprMachineState; 46*8110fa1dSEduardo Habkost DECLARE_OBJ_CHECKERS(SpaprMachineState, SpaprMachineClass, 47*8110fa1dSEduardo Habkost SPAPR_MACHINE, TYPE_SPAPR_MACHINE) 48183930c0SDavid Gibson 4930f4b05bSDavid Gibson typedef enum { 5030f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5130f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5230f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 54ce2918cbSDavid Gibson } SpaprResizeHpt; 5530f4b05bSDavid Gibson 56183930c0SDavid Gibson /** 5733face6bSDavid Gibson * Capabilities 5833face6bSDavid Gibson */ 5933face6bSDavid Gibson 60ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 614e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6229386642SDavid Gibson /* Vector Scalar Extensions */ 634e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 642d1fb9bcSDavid Gibson /* Decimal Floating Point */ 654e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 668f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 678f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 6809114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 6909114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 704be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 714be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 722309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 732309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 74b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 75b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 76c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 77c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 788ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 798ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 808af7e1feSNicholas Piggin /* Implements PAPR FWNMI option */ 818af7e1feSNicholas Piggin #define SPAPR_CAP_FWNMI 0x0A 824e5fe368SSuraj Jitindar Singh /* Num Caps */ 838af7e1feSNicholas Piggin #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1) 844e5fe368SSuraj Jitindar Singh 854e5fe368SSuraj Jitindar Singh /* 864e5fe368SSuraj Jitindar Singh * Capability Values 874e5fe368SSuraj Jitindar Singh */ 884e5fe368SSuraj Jitindar Singh /* Bool Caps */ 894e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 904e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 91399b2896SSuraj Jitindar Singh 92c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 93399b2896SSuraj Jitindar Singh 94399b2896SSuraj Jitindar Singh /* Generic */ 956898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 966898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 976898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 98399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 99c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 100c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 101399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1022d1fb9bcSDavid Gibson 10391067db1SAlexey Kardashevskiy #define FDT_MAX_SIZE 0x100000 10491067db1SAlexey Kardashevskiy 105f1aa45ffSDaniel Henrique Barboza /* 106f1aa45ffSDaniel Henrique Barboza * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken 107d370f9cfSDaniel Henrique Barboza * from Linux kernel arch/powerpc/mm/numa.h. It represents the 108d370f9cfSDaniel Henrique Barboza * amount of associativity domains for non-CPU resources. 109f1aa45ffSDaniel Henrique Barboza * 110f1aa45ffSDaniel Henrique Barboza * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 111f1aa45ffSDaniel Henrique Barboza * array for any non-CPU resource. 112d370f9cfSDaniel Henrique Barboza * 113d370f9cfSDaniel Henrique Barboza * VCPU_ASSOC_SIZE represents the size of ibm,associativity array 114d370f9cfSDaniel Henrique Barboza * for CPUs, which has an extra element (vcpu_id) in the end. 115f1aa45ffSDaniel Henrique Barboza */ 116f1aa45ffSDaniel Henrique Barboza #define MAX_DISTANCE_REF_POINTS 4 117f1aa45ffSDaniel Henrique Barboza #define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1) 118d370f9cfSDaniel Henrique Barboza #define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1) 119f1aa45ffSDaniel Henrique Barboza 120ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 121ce2918cbSDavid Gibson struct SpaprCapabilities { 1224e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 12333face6bSDavid Gibson }; 12433face6bSDavid Gibson 12533face6bSDavid Gibson /** 126ce2918cbSDavid Gibson * SpaprMachineClass: 127183930c0SDavid Gibson */ 128ce2918cbSDavid Gibson struct SpaprMachineClass { 129183930c0SDavid Gibson /*< private >*/ 130183930c0SDavid Gibson MachineClass parent_class; 131183930c0SDavid Gibson 132183930c0SDavid Gibson /*< public >*/ 133224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 134962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 135fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 13657040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 13746f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 13882cffa2eSCédric Le Goater bool legacy_irq_allocation; 13954255c1fSDavid Gibson uint32_t nr_xirqs; 1400a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1413725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1426c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 14329cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 1441052ab67SDavid Gibson hwaddr rma_limit; /* clamp the RMA to this size */ 145a6030d7eSReza Arbab bool pre_5_1_assoc_refpoints; 14682cffa2eSCédric Le Goater 147ce2918cbSDavid Gibson void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 148daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 149daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 150ec132efaSAlexey Kardashevskiy unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 151ec132efaSAlexey Kardashevskiy hwaddr *nv2atsd, Error **errp); 152ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 153ce2918cbSDavid Gibson SpaprCapabilities default_caps; 154ce2918cbSDavid Gibson SpaprIrq *irq; 155183930c0SDavid Gibson }; 15628e02042SDavid Gibson 15728e02042SDavid Gibson /** 158ce2918cbSDavid Gibson * SpaprMachineState: 15928e02042SDavid Gibson */ 160ce2918cbSDavid Gibson struct SpaprMachineState { 16128e02042SDavid Gibson /*< private >*/ 16228e02042SDavid Gibson MachineState parent_obj; 16328e02042SDavid Gibson 164ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 165ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 166ce2918cbSDavid Gibson struct SpaprNvram *nvram; 167ce2918cbSDavid Gibson SpaprRtcState rtc; 1680d09e41aSPaolo Bonzini 169ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1700d09e41aSPaolo Bonzini void *htab; 1714be21d56SDavid Gibson uint32_t htab_shift; 1729861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 173ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1740b0b8310SDavid Gibson 1750d09e41aSPaolo Bonzini hwaddr rma_size; 176fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 177fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 178fea35ca4SAlexey Kardashevskiy void *fdt_blob; 179a19f7fb0SDavid Gibson long kernel_size; 180a19f7fb0SDavid Gibson bool kernel_le; 18187262806SAlexey Kardashevskiy uint64_t kernel_addr; 182a19f7fb0SDavid Gibson uint32_t initrd_base; 183a19f7fb0SDavid Gibson long initrd_size; 184880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 18598a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1860d09e41aSPaolo Bonzini bool has_graphics; 187fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1880d09e41aSPaolo Bonzini 1890d09e41aSPaolo Bonzini Notifier epow_notifier; 190ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 191ffbb1705SMichael Roth bool use_hotplug_event_source; 192ce2918cbSDavid Gibson SpaprEventSource *event_sources; 1934be21d56SDavid Gibson 1947843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 195daa36379SDavid Gibson bool cas_pre_isa3_guest; 196ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 197ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1987843c0d6SDavid Gibson uint32_t max_compat_pvr; 1997843c0d6SDavid Gibson 2004be21d56SDavid Gibson /* Migration state */ 2014be21d56SDavid Gibson int htab_save_index; 2024be21d56SDavid Gibson bool htab_first_pass; 203e68cb8b4SAlexey Kardashevskiy int htab_fd; 20446503c2bSMichael Roth 2050cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 2060cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 2070cffce56SDavid Gibson * occurs during the unplug process. */ 208ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 2090cffce56SDavid Gibson 2108af7e1feSNicholas Piggin /* State related to FWNMI option */ 2118af7e1feSNicholas Piggin 212edfdbf9cSNicholas Piggin /* System Reset and Machine Check Notification Routine addresses 2138af7e1feSNicholas Piggin * registered by "ibm,nmi-register" RTAS call. 2149ac703acSAravinda Prasad */ 215edfdbf9cSNicholas Piggin target_ulong fwnmi_system_reset_addr; 2168af7e1feSNicholas Piggin target_ulong fwnmi_machine_check_addr; 2178af7e1feSNicholas Piggin 2188af7e1feSNicholas Piggin /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 2198af7e1feSNicholas Piggin * set to -1 if a FWNMI machine check is not in progress, else is set to 2208af7e1feSNicholas Piggin * the CPU that was delivered the machine check, and is set back to -1 2218af7e1feSNicholas Piggin * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 2228af7e1feSNicholas Piggin * to synchronize other CPUs. 2238af7e1feSNicholas Piggin */ 2248af7e1feSNicholas Piggin int fwnmi_machine_check_interlock; 2258af7e1feSNicholas Piggin QemuCond fwnmi_machine_check_interlock_cond; 2269ac703acSAravinda Prasad 22728e02042SDavid Gibson /*< public >*/ 22828e02042SDavid Gibson char *kvm_type; 22927461d69SPrasad J Pandit char *host_model; 23027461d69SPrasad J Pandit char *host_serial; 231852ad27eSCédric Le Goater 23282cffa2eSCédric Le Goater int32_t irq_map_nr; 23382cffa2eSCédric Le Goater unsigned long *irq_map; 234ce2918cbSDavid Gibson SpaprIrq *irq; 235872ff3deSCédric Le Goater qemu_irq *qirqs; 23681106dddSDavid Gibson SpaprInterruptController *active_intc; 23781106dddSDavid Gibson ICSState *ics; 23881106dddSDavid Gibson SpaprXive *xive; 23933face6bSDavid Gibson 2404e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 241ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 242ec132efaSAlexey Kardashevskiy 243ec132efaSAlexey Kardashevskiy unsigned gpu_numa_id; 2440fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 2452500fb42SAravinda Prasad 246f1aa45ffSDaniel Henrique Barboza uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE]; 247f1aa45ffSDaniel Henrique Barboza 2482500fb42SAravinda Prasad Error *fwnmi_migration_blocker; 24928e02042SDavid Gibson }; 2500d09e41aSPaolo Bonzini 2510d09e41aSPaolo Bonzini #define H_SUCCESS 0 2520d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2530d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2540d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2550d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2560d09e41aSPaolo Bonzini #define H_PARTIAL 5 2570d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2580d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2590d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2600d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2610d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2620d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2630d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2640d09e41aSPaolo Bonzini is a good time to retry */ 2650d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2660d09e41aSPaolo Bonzini is a good time to retry */ 2670d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2680d09e41aSPaolo Bonzini is a good time to retry */ 2690d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2700d09e41aSPaolo Bonzini is a good time to retry */ 2710d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2720d09e41aSPaolo Bonzini is a good time to retry */ 2730d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2740d09e41aSPaolo Bonzini is a good time to retry */ 2750d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2760d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2770d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2780d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2790d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2800d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2810d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2820d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2830d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2840d09e41aSPaolo Bonzini #define H_NO_MEM -9 2850d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2860d09e41aSPaolo Bonzini #define H_PERMISSION -11 2870d09e41aSPaolo Bonzini #define H_DROPPED -12 2880d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2890d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2900d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2910d09e41aSPaolo Bonzini #define H_RESOURCE -16 2920d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2930d09e41aSPaolo Bonzini #define H_RH_PARM -18 2940d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2950d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2960d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2970d09e41aSPaolo Bonzini #define H_RT_PARM -22 2980d09e41aSPaolo Bonzini #define H_ST_PARM -23 2990d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 3000d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 3010d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 3020d09e41aSPaolo Bonzini #define H_MEM_PARM -28 3030d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 3040d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 3050d09e41aSPaolo Bonzini #define H_PORT_PARM -31 3060d09e41aSPaolo Bonzini #define H_MCG_PARM -32 3070d09e41aSPaolo Bonzini #define H_VL_PARM -33 3080d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 3090d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 3100d09e41aSPaolo Bonzini 3110d09e41aSPaolo Bonzini #define H_MASK_PARM -37 3120d09e41aSPaolo Bonzini #define H_MCG_FULL -38 3130d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 3140d09e41aSPaolo Bonzini #define H_P_COUNTER -40 3150d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 3160d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 3170d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 3180d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 3190d09e41aSPaolo Bonzini #define H_R_STATE -45 3200d09e41aSPaolo Bonzini #define H_RESCINDEND -46 32142561bf2SAnton Blanchard #define H_P2 -55 32242561bf2SAnton Blanchard #define H_P3 -56 32342561bf2SAnton Blanchard #define H_P4 -57 32442561bf2SAnton Blanchard #define H_P5 -58 32542561bf2SAnton Blanchard #define H_P6 -59 32642561bf2SAnton Blanchard #define H_P7 -60 32742561bf2SAnton Blanchard #define H_P8 -61 32842561bf2SAnton Blanchard #define H_P9 -62 329b5fca656SShivaprasad G Bhat #define H_OVERLAP -68 33042561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 3310d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 3320d09e41aSPaolo Bonzini 3330d09e41aSPaolo Bonzini 3340d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 3350d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 3360d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 3370d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 3380d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 3390d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3400d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3410d09e41aSPaolo Bonzini */ 3420d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3430d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3440d09e41aSPaolo Bonzini 3450d09e41aSPaolo Bonzini /* Flags */ 3460d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3470d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3480d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3490d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3500d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3510d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3520d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3530d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3540d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3550d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3560d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3570d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3580d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3590d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3600d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3610d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3620d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3630d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3640d09e41aSPaolo Bonzini 365a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 366a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 367a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 368a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 369a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 370a46622fdSAlexey Kardashevskiy 371a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 37242561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 37342561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 37442561bf2SAnton Blanchard 3750d09e41aSPaolo Bonzini /* VASI States */ 3760d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3770d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3780d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3790d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3800d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3810d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3820d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3830d09e41aSPaolo Bonzini 3840d09e41aSPaolo Bonzini /* DABRX flags */ 3850d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3860d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3870d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3880d09e41aSPaolo Bonzini 3898acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3908acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3918acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3928acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3938acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3948acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3958acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3968acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 397c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 398399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 3998acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 4008acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 4018acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 402399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 4038acc2ae5SSuraj Jitindar Singh 4040d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 4050d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 4060d09e41aSPaolo Bonzini 4070d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 4080d09e41aSPaolo Bonzini #define H_REMOVE 0x04 4090d09e41aSPaolo Bonzini #define H_ENTER 0x08 4100d09e41aSPaolo Bonzini #define H_READ 0x0c 4110d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 4120d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 4130d09e41aSPaolo Bonzini #define H_PROTECT 0x18 4140d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 4150d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 4160d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 4170d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 4180d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 4190d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 4200d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 4210d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 4220d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 4230d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 4240d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 4250d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 4260d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 4270d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 4280d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 4290d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 4300d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 4310d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 4320d09e41aSPaolo Bonzini #define H_EOI 0x64 4330d09e41aSPaolo Bonzini #define H_CPPR 0x68 4340d09e41aSPaolo Bonzini #define H_IPI 0x6c 4350d09e41aSPaolo Bonzini #define H_IPOLL 0x70 4360d09e41aSPaolo Bonzini #define H_XIRR 0x74 4370d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 4380d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 4390d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4400d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4410d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4420d09e41aSPaolo Bonzini #define H_PROD 0xE8 4430d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4440d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4450d09e41aSPaolo Bonzini #define H_PURR 0xF4 4460d09e41aSPaolo Bonzini #define H_PIC 0xF8 4470d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4480d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4490d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4500d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4510d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4520d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4530d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4540d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4550d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4560d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4570d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4580d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4590d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4600d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4610d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4620d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4630d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4640d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4650d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4660d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4670d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4680d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4690d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4700d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4710d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4720d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4730d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4740d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4750d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4760d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4770d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4780d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4790d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4800d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4810d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4820d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4830d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4840d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4850d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4860d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4870d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4880d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4890d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4900d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 491c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4920d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4930d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4940d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4950d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4960d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4970d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4980d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4990d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 5000d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 5010d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 5020d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 5030d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 5040d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 5050d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 5060d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 5070d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 5080d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 5090d09e41aSPaolo Bonzini #define H_JOIN 0x298 5100d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 5110d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 5120d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 5130d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 5140d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 515c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 5165d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 5174d9392beSThomas Huth #define H_RANDOM 0x300 51842561bf2SAnton Blanchard #define H_SET_MODE 0x31C 51930f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 52030f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 521d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 522d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 523d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 5241c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 52523bcd5ebSCédric Le Goater 52623bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 52723bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 52823bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 52923bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 53023bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 53123bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 53223bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 53323bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 53423bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 53523bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 53623bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 537b5fca656SShivaprasad G Bhat #define H_SCM_READ_METADATA 0x3E4 538b5fca656SShivaprasad G Bhat #define H_SCM_WRITE_METADATA 0x3E8 539b5fca656SShivaprasad G Bhat #define H_SCM_BIND_MEM 0x3EC 540b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_MEM 0x3F0 541b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_ALL 0x3FC 54223bcd5ebSCédric Le Goater 543b5fca656SShivaprasad G Bhat #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 5440d09e41aSPaolo Bonzini 5450d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5460d09e41aSPaolo Bonzini * as well. 5470d09e41aSPaolo Bonzini * 5480d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 549498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 550498cd995SGreg Kurz * for "platform-specific" hcalls. 5510d09e41aSPaolo Bonzini */ 5520d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5530d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5540d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5552a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5562a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 557fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 558fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 5590d09e41aSPaolo Bonzini 5600fb6bd07SMichael Roth /* 5610fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 5620fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 5630fb6bd07SMichael Roth */ 5640fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 5650fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 5660fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 5670fb6bd07SMichael Roth 5680fb6bd07SMichael Roth 569ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 5702a6593cbSAlexey Kardashevskiy uint32_t version_id; 571ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 5722a6593cbSAlexey Kardashevskiy 5730d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 574aaf87c66SThomas Huth do { \ 575aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 576aaf87c66SThomas Huth } while (0) 5770d09e41aSPaolo Bonzini 578ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 5790d09e41aSPaolo Bonzini target_ulong opcode, 5800d09e41aSPaolo Bonzini target_ulong *args); 5810d09e41aSPaolo Bonzini 5820d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5830d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5840d09e41aSPaolo Bonzini target_ulong *args); 5850d09e41aSPaolo Bonzini 58691067db1SAlexey Kardashevskiy target_ulong do_client_architecture_support(PowerPCCPU *cpu, 58791067db1SAlexey Kardashevskiy SpaprMachineState *spapr, 58891067db1SAlexey Kardashevskiy target_ulong addr, 58991067db1SAlexey Kardashevskiy target_ulong fdt_bufsize); 59091067db1SAlexey Kardashevskiy 59103ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 59203ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 59303ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 59403ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 59503ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 59603ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 59703ef074cSNicholas Piggin 598ee954280SGavin Shan /* ibm,set-eeh-option */ 599ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 600ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 601ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 602ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 603ee954280SGavin Shan 604ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 605ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 606ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 607ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 608ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 609ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 610ee954280SGavin Shan 611ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 612ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 613ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 614ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 615ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 616ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 617ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 618ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 619ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 620ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 621ee954280SGavin Shan 622ee954280SGavin Shan /* ibm,set-slot-reset */ 623ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 624ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 625ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 626ee954280SGavin Shan 627ee954280SGavin Shan /* ibm,slot-error-detail */ 628ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 629ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 630ee954280SGavin Shan 631a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 632a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 633a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 634a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 635a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 636a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 6373ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 6389d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 6393ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 640c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 641a64d325dSAlexey Kardashevskiy 642ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 643ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 644ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 645ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 646ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 647ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 648ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 649ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 650ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 651ae4de14cSAlexey Kardashevskiy 6523a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 6533a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 6543a3b8502SAlexey Kardashevskiy 6553a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 6563a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 6573a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 6583a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 6593a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 6603a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 6613a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 6623a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 6633a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 6643a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 6653a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 6663a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 6673a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 6683a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 6693a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 6703a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 6713a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 6723a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 6733a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 6743a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 6753a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 6763a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 6773a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 6783a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 6793a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 6803a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 6813a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 6823a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 6833a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 6843a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 6853a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6863a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 687ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 688ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 689ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 690ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 691ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 692ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 693ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 694ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 695ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 696ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 69793eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 698f03496bcSAravinda Prasad #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 699f03496bcSAravinda Prasad #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 7003a3b8502SAlexey Kardashevskiy 701f03496bcSAravinda Prasad #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 7023a3b8502SAlexey Kardashevskiy 7033052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 7043b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 7053052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 706b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 7073052d951SSam bobroff 7088c8639dfSMike Day /* RTAS indicator/sensor types 7098c8639dfSMike Day * 7108c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 7118c8639dfSMike Day * 7128c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 7138c8639dfSMike Day */ 7148c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 7158c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 7168c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 7178c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 7188c8639dfSMike Day 7193052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 7203052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 7213052d951SSam bobroff */ 7223052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 7233052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 7243052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 7253052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 7263052d951SSam bobroff 7274fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 7284fe822e0SAlexey Kardashevskiy { 7294fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 7304fe822e0SAlexey Kardashevskiy } 7314fe822e0SAlexey Kardashevskiy 7320d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 7330d09e41aSPaolo Bonzini { 734fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 7350d09e41aSPaolo Bonzini } 7360d09e41aSPaolo Bonzini 737a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 738a14aa92bSGavin Shan { 739a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 740a14aa92bSGavin Shan } 741a14aa92bSGavin Shan 7420d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 7430d09e41aSPaolo Bonzini { 744ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 7450d09e41aSPaolo Bonzini } 7460d09e41aSPaolo Bonzini 747ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 748210b580bSAnthony Liguori uint32_t token, 7490d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 7500d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7513a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 752ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 7530d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 7540d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7553f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 756ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 7570d09e41aSPaolo Bonzini 7580d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 7590d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 7600d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 7610d09e41aSPaolo Bonzini 7620d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 7634290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 764c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 765c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 766d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 767c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 7680d09e41aSPaolo Bonzini 7694dba8722SAlexey Kardashevskiy #define RTAS_SIZE 2048 7700d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 7710d09e41aSPaolo Bonzini 77281fe70e4SAravinda Prasad /* Offset from rtas-base where error log is placed */ 77381fe70e4SAravinda Prasad #define RTAS_ERROR_LOG_OFFSET 0x30 77481fe70e4SAravinda Prasad 77579853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 77679853e18STyrel Datwyler 777bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 778bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 779bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 780bb2d8ab6SGreg Kurz */ 7815c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 782bb2d8ab6SGreg Kurz { 783bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 784bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 785bb2d8ab6SGreg Kurz } 786bb2d8ab6SGreg Kurz 787ce2918cbSDavid Gibson typedef struct SpaprTceTable SpaprTceTable; 7880d09e41aSPaolo Bonzini 789a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 790*8110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(SpaprTceTable, SPAPR_TCE_TABLE, 791*8110fa1dSEduardo Habkost TYPE_SPAPR_TCE_TABLE) 792a83000f5SAnthony Liguori 7931221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 794*8110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 795*8110fa1dSEduardo Habkost TYPE_SPAPR_IOMMU_MEMORY_REGION) 7961221a474SAlexey Kardashevskiy 797ce2918cbSDavid Gibson struct SpaprTceTable { 798a83000f5SAnthony Liguori DeviceState parent; 799a83000f5SAnthony Liguori uint32_t liobn; 800a83000f5SAnthony Liguori uint32_t nb_table; 8011b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 802650f33adSAlexey Kardashevskiy uint32_t page_shift; 803a83000f5SAnthony Liguori uint64_t *table; 804a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 805a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 806a83000f5SAnthony Liguori bool bypass; 8076a81dd17SDavid Gibson bool need_vfio; 8085f366667SAlexey Kardashevskiy bool skipping_replay; 809a83000f5SAnthony Liguori int fd; 8103df9d748SAlexey Kardashevskiy MemoryRegion root; 8113df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 812ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 813ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 814a83000f5SAnthony Liguori }; 815a83000f5SAnthony Liguori 816ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 81731fe14d1SNathan Fontenot 818ce2918cbSDavid Gibson struct SpaprEventLogEntry { 819fd38804bSDaniel Henrique Barboza uint32_t summary; 820fd38804bSDaniel Henrique Barboza uint32_t extended_length; 821fd38804bSDaniel Henrique Barboza void *extended_log; 822ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 82331fe14d1SNathan Fontenot }; 82431fe14d1SNathan Fontenot 8250c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 826ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 827ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 828ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 8298897ea5aSDavid Gibson void spapr_setup_hpt(SpaprMachineState *spapr); 830ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 831ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 832ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 833df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 834df7625d4SAlexey Kardashevskiy uint32_t nb_table); 835ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 836ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 837c10325d6SDavid Gibson 838ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 8390d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 8400d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 8410d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 842ce2918cbSDavid Gibson SpaprTceTable *tcet); 843eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 844ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 845ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 846ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 8477a36ae7aSBharata B Rao uint32_t count); 848ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 8497a36ae7aSBharata B Rao uint32_t count); 850ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 851afdbd403SBharata B Rao uint32_t count, uint32_t index); 852ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 853afdbd403SBharata B Rao uint32_t count, uint32_t index); 8540b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 855ce2918cbSDavid Gibson void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 8562772cf6bSDavid Gibson Error **errp); 857ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 858ad334d89SGreg Kurz void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 859ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 860a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 861a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 86281fe70e4SAravinda Prasad void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 86328df36a1SDavid Gibson 86462d38c9bSGreg Kurz /* DRC callbacks. */ 86531834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 866ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 867345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 86831834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 869ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 87062d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 871bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 872ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 873bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 87431834723SDaniel Henrique Barboza 875ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 876ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 87728df36a1SDavid Gibson 878147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 8790d09e41aSPaolo Bonzini 880e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 881db4ef288SBharata B Rao 8824a1c9cf0SBharata B Rao /* 8834a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 8844a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 8854a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 8864a1c9cf0SBharata B Rao */ 8874a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 8884a1c9cf0SBharata B Rao 889ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 890ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 8914a1c9cf0SBharata B Rao 89203d196b7SBharata B Rao /* 89303d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 89403d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 89503d196b7SBharata B Rao */ 89603d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 89703d196b7SBharata B Rao 89803d196b7SBharata B Rao /* 899d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 900d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 90103d196b7SBharata B Rao */ 90203d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 903d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 904d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 9050911a60cSLeonardo Bras #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 90603d196b7SBharata B Rao 9071c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 9081c7ad77eSNicholas Piggin 9090b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 9100b0b8310SDavid Gibson 91114bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 912648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 9132e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 9142e886fb3SSam Bobroff 9154e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 9164e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 9174e5fe368SSuraj Jitindar Singh 91833face6bSDavid Gibson /* 91933face6bSDavid Gibson * Handling of optional capabilities 92033face6bSDavid Gibson */ 9214e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 9224e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 9234e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 9248f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 92509114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 9264be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 92764d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 928b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 929c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 9308ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 9319d953ce4SAravinda Prasad extern const VMStateDescription vmstate_spapr_cap_fwnmi; 932be85537dSDavid Gibson 933ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 93433face6bSDavid Gibson { 9354e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 93633face6bSDavid Gibson } 93733face6bSDavid Gibson 938ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 939ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 940ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 94140c2281cSMarkus Armbruster void spapr_caps_add_properties(SpaprMachineClass *smc); 942ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 94333face6bSDavid Gibson 944ce2918cbSDavid Gibson void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 945123eec65SDavid Gibson Error **errp); 946db592b5bSCédric Le Goater /* 947db592b5bSCédric Le Goater * XIVE definitions 948db592b5bSCédric Le Goater */ 949db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 950db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 951db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 952123eec65SDavid Gibson 95300fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 95481fe70e4SAravinda Prasad hwaddr spapr_get_rtas_addr(void); 9552a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 956