12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 40d09e41aSPaolo Bonzini #include "sysemu/dma.h" 528e02042SDavid Gibson #include "hw/boards.h" 60d09e41aSPaolo Bonzini #include "hw/ppc/xics.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 100d09e41aSPaolo Bonzini 110d09e41aSPaolo Bonzini struct VIOsPAPRBus; 120d09e41aSPaolo Bonzini struct sPAPRPHBState; 130d09e41aSPaolo Bonzini struct sPAPRNVRAM; 1431fe14d1SNathan Fontenot typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15ffbb1705SMichael Roth typedef struct sPAPREventSource sPAPREventSource; 160d09e41aSPaolo Bonzini 174be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 181b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 194be21d56SDavid Gibson 20afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 21afd10a0fSBharata B Rao 22147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 23147ff807SCédric Le Goater 24147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 25147ff807SCédric Le Goater OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 26147ff807SCédric Le Goater 27147ff807SCédric Le Goater typedef struct sPAPRRTCState sPAPRRTCState; 28147ff807SCédric Le Goater struct sPAPRRTCState { 29147ff807SCédric Le Goater /*< private >*/ 30147ff807SCédric Le Goater DeviceState parent_obj; 31147ff807SCédric Le Goater int64_t ns_offset; 32147ff807SCédric Le Goater }; 33147ff807SCédric Le Goater 340cffce56SDavid Gibson typedef struct sPAPRDIMMState sPAPRDIMMState; 35183930c0SDavid Gibson typedef struct sPAPRMachineClass sPAPRMachineClass; 3628e02042SDavid Gibson 3728e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 3828e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 3928e02042SDavid Gibson OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 40183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 41183930c0SDavid Gibson OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 42183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 43183930c0SDavid Gibson OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 44183930c0SDavid Gibson 45183930c0SDavid Gibson /** 46183930c0SDavid Gibson * sPAPRMachineClass: 47183930c0SDavid Gibson */ 48183930c0SDavid Gibson struct sPAPRMachineClass { 49183930c0SDavid Gibson /*< private >*/ 50183930c0SDavid Gibson MachineClass parent_class; 51183930c0SDavid Gibson 52183930c0SDavid Gibson /*< public >*/ 53224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 5457040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 553daa4a9fSThomas Huth const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 566737d9adSDavid Gibson void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 57daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 58daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 596737d9adSDavid Gibson unsigned n_dma, uint32_t *liobns, Error **errp); 60183930c0SDavid Gibson }; 6128e02042SDavid Gibson 6228e02042SDavid Gibson /** 6328e02042SDavid Gibson * sPAPRMachineState: 6428e02042SDavid Gibson */ 6528e02042SDavid Gibson struct sPAPRMachineState { 6628e02042SDavid Gibson /*< private >*/ 6728e02042SDavid Gibson MachineState parent_obj; 6828e02042SDavid Gibson 690d09e41aSPaolo Bonzini struct VIOsPAPRBus *vio_bus; 700d09e41aSPaolo Bonzini QLIST_HEAD(, sPAPRPHBState) phbs; 710d09e41aSPaolo Bonzini struct sPAPRNVRAM *nvram; 72681bfadeSCédric Le Goater ICSState *ics; 73147ff807SCédric Le Goater sPAPRRTCState rtc; 740d09e41aSPaolo Bonzini 750d09e41aSPaolo Bonzini void *htab; 764be21d56SDavid Gibson uint32_t htab_shift; 779861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 780d09e41aSPaolo Bonzini hwaddr rma_size; 790d09e41aSPaolo Bonzini int vrma_adjust; 80b7d1f77aSBenjamin Herrenschmidt ssize_t rtas_size; 81b7d1f77aSBenjamin Herrenschmidt void *rtas_blob; 82a19f7fb0SDavid Gibson long kernel_size; 83a19f7fb0SDavid Gibson bool kernel_le; 84a19f7fb0SDavid Gibson uint32_t initrd_base; 85a19f7fb0SDavid Gibson long initrd_size; 86880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 8798a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 880d09e41aSPaolo Bonzini bool has_graphics; 890d09e41aSPaolo Bonzini 900d09e41aSPaolo Bonzini Notifier epow_notifier; 9131fe14d1SNathan Fontenot QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 92ffbb1705SMichael Roth bool use_hotplug_event_source; 93ffbb1705SMichael Roth sPAPREventSource *event_sources; 944be21d56SDavid Gibson 95*7843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 96*7843c0d6SDavid Gibson bool cas_reboot; 97*7843c0d6SDavid Gibson bool cas_legacy_guest_workaround; 98*7843c0d6SDavid Gibson sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 99*7843c0d6SDavid Gibson sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 100*7843c0d6SDavid Gibson uint32_t max_compat_pvr; 101*7843c0d6SDavid Gibson 1024be21d56SDavid Gibson /* Migration state */ 1034be21d56SDavid Gibson int htab_save_index; 1044be21d56SDavid Gibson bool htab_first_pass; 105e68cb8b4SAlexey Kardashevskiy int htab_fd; 10646503c2bSMichael Roth 1070cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1080cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1090cffce56SDavid Gibson * occurs during the unplug process. */ 1100cffce56SDavid Gibson QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 1110cffce56SDavid Gibson 11228e02042SDavid Gibson /*< public >*/ 11328e02042SDavid Gibson char *kvm_type; 1144a1c9cf0SBharata B Rao MemoryHotplugState hotplug_memory; 115852ad27eSCédric Le Goater 1165bc8d26dSCédric Le Goater const char *icp_type; 11728e02042SDavid Gibson }; 1180d09e41aSPaolo Bonzini 1190d09e41aSPaolo Bonzini #define H_SUCCESS 0 1200d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 1210d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 1220d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 1230d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 1240d09e41aSPaolo Bonzini #define H_PARTIAL 5 1250d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 1260d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 1270d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 1280d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 1290d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 1300d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 1310d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 1320d09e41aSPaolo Bonzini is a good time to retry */ 1330d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 1340d09e41aSPaolo Bonzini is a good time to retry */ 1350d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 1360d09e41aSPaolo Bonzini is a good time to retry */ 1370d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 1380d09e41aSPaolo Bonzini is a good time to retry */ 1390d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 1400d09e41aSPaolo Bonzini is a good time to retry */ 1410d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 1420d09e41aSPaolo Bonzini is a good time to retry */ 1430d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 1440d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 1450d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 1460d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 1470d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 1480d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 1490d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 1500d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 1510d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 1520d09e41aSPaolo Bonzini #define H_NO_MEM -9 1530d09e41aSPaolo Bonzini #define H_AUTHORITY -10 1540d09e41aSPaolo Bonzini #define H_PERMISSION -11 1550d09e41aSPaolo Bonzini #define H_DROPPED -12 1560d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 1570d09e41aSPaolo Bonzini #define H_DEST_PARM -14 1580d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 1590d09e41aSPaolo Bonzini #define H_RESOURCE -16 1600d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 1610d09e41aSPaolo Bonzini #define H_RH_PARM -18 1620d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 1630d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 1640d09e41aSPaolo Bonzini #define H_EQ_PARM -21 1650d09e41aSPaolo Bonzini #define H_RT_PARM -22 1660d09e41aSPaolo Bonzini #define H_ST_PARM -23 1670d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 1680d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 1690d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 1700d09e41aSPaolo Bonzini #define H_MEM_PARM -28 1710d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 1720d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 1730d09e41aSPaolo Bonzini #define H_PORT_PARM -31 1740d09e41aSPaolo Bonzini #define H_MCG_PARM -32 1750d09e41aSPaolo Bonzini #define H_VL_PARM -33 1760d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 1770d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 1780d09e41aSPaolo Bonzini 1790d09e41aSPaolo Bonzini #define H_MASK_PARM -37 1800d09e41aSPaolo Bonzini #define H_MCG_FULL -38 1810d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 1820d09e41aSPaolo Bonzini #define H_P_COUNTER -40 1830d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 1840d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 1850d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 1860d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 1870d09e41aSPaolo Bonzini #define H_R_STATE -45 1880d09e41aSPaolo Bonzini #define H_RESCINDEND -46 18942561bf2SAnton Blanchard #define H_P2 -55 19042561bf2SAnton Blanchard #define H_P3 -56 19142561bf2SAnton Blanchard #define H_P4 -57 19242561bf2SAnton Blanchard #define H_P5 -58 19342561bf2SAnton Blanchard #define H_P6 -59 19442561bf2SAnton Blanchard #define H_P7 -60 19542561bf2SAnton Blanchard #define H_P8 -61 19642561bf2SAnton Blanchard #define H_P9 -62 19742561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 1980d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 1990d09e41aSPaolo Bonzini 2000d09e41aSPaolo Bonzini 2010d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 2020d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 2030d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 2040d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 2050d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 2060d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 2070d09e41aSPaolo Bonzini * way to check for the long_busy return codes 2080d09e41aSPaolo Bonzini */ 2090d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 2100d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 2110d09e41aSPaolo Bonzini 2120d09e41aSPaolo Bonzini /* Flags */ 2130d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 2140d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 2150d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 2160d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 2170d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 2180d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 2190d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 2200d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 2210d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 2220d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 2230d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 2240d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 2250d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 2260d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 2270d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 2280d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 2290d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 2300d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 2310d09e41aSPaolo Bonzini 232a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 233a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 234a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 235a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 236a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 237a46622fdSAlexey Kardashevskiy 238a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 23942561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 24042561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 24142561bf2SAnton Blanchard 2420d09e41aSPaolo Bonzini /* VASI States */ 2430d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 2440d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 2450d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 2460d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 2470d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 2480d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 2490d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 2500d09e41aSPaolo Bonzini 2510d09e41aSPaolo Bonzini /* DABRX flags */ 2520d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 2530d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 2540d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 2550d09e41aSPaolo Bonzini 2560d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 2570d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 2580d09e41aSPaolo Bonzini 2590d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 2600d09e41aSPaolo Bonzini #define H_REMOVE 0x04 2610d09e41aSPaolo Bonzini #define H_ENTER 0x08 2620d09e41aSPaolo Bonzini #define H_READ 0x0c 2630d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 2640d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 2650d09e41aSPaolo Bonzini #define H_PROTECT 0x18 2660d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 2670d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 2680d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 2690d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 2700d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 2710d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 2720d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 2730d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 2740d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 2750d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 2760d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 2770d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 2780d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 2790d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 2800d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 2810d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 2820d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 2830d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 2840d09e41aSPaolo Bonzini #define H_EOI 0x64 2850d09e41aSPaolo Bonzini #define H_CPPR 0x68 2860d09e41aSPaolo Bonzini #define H_IPI 0x6c 2870d09e41aSPaolo Bonzini #define H_IPOLL 0x70 2880d09e41aSPaolo Bonzini #define H_XIRR 0x74 2890d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 2900d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 2910d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 2920d09e41aSPaolo Bonzini #define H_CEDE 0xE0 2930d09e41aSPaolo Bonzini #define H_CONFER 0xE4 2940d09e41aSPaolo Bonzini #define H_PROD 0xE8 2950d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 2960d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 2970d09e41aSPaolo Bonzini #define H_PURR 0xF4 2980d09e41aSPaolo Bonzini #define H_PIC 0xF8 2990d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 3000d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 3010d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 3020d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 3030d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 3040d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 3050d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 3060d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 3070d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 3080d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 3090d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 3100d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 3110d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 3120d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 3130d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 3140d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 3150d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 3160d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 3170d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 3180d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 3190d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 3200d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 3210d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 3220d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 3230d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 3240d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 3250d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 3260d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 3270d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 3280d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 3290d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 3300d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 3310d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 3320d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 3330d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 3340d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 3350d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 3360d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 3370d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 3380d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 3390d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 3400d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 3410d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 3420d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 3430d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 3440d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 3450d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 3460d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 3470d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 3480d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 3490d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 3500d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 3510d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 3520d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 3530d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 3540d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 3550d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 3560d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 3570d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 3580d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 3590d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 3600d09e41aSPaolo Bonzini #define H_JOIN 0x298 3610d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 3620d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 3630d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 3640d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 3650d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 3665d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 3674d9392beSThomas Huth #define H_RANDOM 0x300 36842561bf2SAnton Blanchard #define H_SET_MODE 0x31C 369d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 370d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 371d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 3721c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 3731c7ad77eSNicholas Piggin #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 3740d09e41aSPaolo Bonzini 3750d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 3760d09e41aSPaolo Bonzini * as well. 3770d09e41aSPaolo Bonzini * 3780d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 3790d09e41aSPaolo Bonzini * So far we just need one for H_RTAS, but in future we'll need more 3800d09e41aSPaolo Bonzini * for extensions like virtio. We put those into the 0xf000-0xfffc 3810d09e41aSPaolo Bonzini * range which is reserved by PAPR for "platform-specific" hcalls. 3820d09e41aSPaolo Bonzini */ 3830d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 3840d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 3850d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 3862a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 3872a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 3882a6593cbSAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 3890d09e41aSPaolo Bonzini 3902a6593cbSAlexey Kardashevskiy typedef struct sPAPRDeviceTreeUpdateHeader { 3912a6593cbSAlexey Kardashevskiy uint32_t version_id; 3922a6593cbSAlexey Kardashevskiy } sPAPRDeviceTreeUpdateHeader; 3932a6593cbSAlexey Kardashevskiy 3940d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 395aaf87c66SThomas Huth do { \ 396aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 397aaf87c66SThomas Huth } while (0) 3980d09e41aSPaolo Bonzini 39928e02042SDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 4000d09e41aSPaolo Bonzini target_ulong opcode, 4010d09e41aSPaolo Bonzini target_ulong *args); 4020d09e41aSPaolo Bonzini 4030d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 4040d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 4050d09e41aSPaolo Bonzini target_ulong *args); 4060d09e41aSPaolo Bonzini 407ee954280SGavin Shan /* ibm,set-eeh-option */ 408ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 409ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 410ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 411ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 412ee954280SGavin Shan 413ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 414ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 415ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 416ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 417ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 418ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 419ee954280SGavin Shan 420ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 421ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 422ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 423ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 424ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 425ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 426ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 427ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 428ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 429ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 430ee954280SGavin Shan 431ee954280SGavin Shan /* ibm,set-slot-reset */ 432ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 433ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 434ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 435ee954280SGavin Shan 436ee954280SGavin Shan /* ibm,slot-error-detail */ 437ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 438ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 439ee954280SGavin Shan 440a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 441a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 442a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 443a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 444a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 445a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 4463ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 4479d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 4483ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 449c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 450a64d325dSAlexey Kardashevskiy 451ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 452ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 453ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 454ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 455ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 456ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 457ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 458ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 459ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 460ae4de14cSAlexey Kardashevskiy 4613a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 4623a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 4633a3b8502SAlexey Kardashevskiy 4643a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 4653a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 4663a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 4673a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 4683a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 4693a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 4703a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 4713a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 4723a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 4733a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 4743a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 4753a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 4763a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 4773a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 4783a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 4793a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 4803a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 4813a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 4823a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 4833a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 4843a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 4853a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 4863a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 4873a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 4883a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 4893a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 4903a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 4913a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 4923a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 4933a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 4943a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 4953a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 496ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 497ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 498ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 499ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 500ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 501ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 502ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 503ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 504ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 505ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 5063a3b8502SAlexey Kardashevskiy 507ae4de14cSAlexey Kardashevskiy #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 5083a3b8502SAlexey Kardashevskiy 5093052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 5103b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 5113052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 512b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 5133052d951SSam bobroff 5148c8639dfSMike Day /* RTAS indicator/sensor types 5158c8639dfSMike Day * 5168c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 5178c8639dfSMike Day * 5188c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 5198c8639dfSMike Day */ 5208c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 5218c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 5228c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 5238c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 5248c8639dfSMike Day 5253052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 5263052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 5273052d951SSam bobroff */ 5283052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 5293052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 5303052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 5313052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 5323052d951SSam bobroff 5334fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 5344fe822e0SAlexey Kardashevskiy { 5354fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 5364fe822e0SAlexey Kardashevskiy } 5374fe822e0SAlexey Kardashevskiy 5380d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 5390d09e41aSPaolo Bonzini { 540fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 5410d09e41aSPaolo Bonzini } 5420d09e41aSPaolo Bonzini 543a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 544a14aa92bSGavin Shan { 545a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 546a14aa92bSGavin Shan } 547a14aa92bSGavin Shan 5480d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 5490d09e41aSPaolo Bonzini { 550ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 5510d09e41aSPaolo Bonzini } 5520d09e41aSPaolo Bonzini 55328e02042SDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 554210b580bSAnthony Liguori uint32_t token, 5550d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 5560d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 5573a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 55828e02042SDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 5590d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 5600d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 5613f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 5622cac78c1SDavid Gibson void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 5630d09e41aSPaolo Bonzini 5640d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 5650d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 5660d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 5670d09e41aSPaolo Bonzini 5680d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 5694290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 570c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 571c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 572d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 573c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 5740d09e41aSPaolo Bonzini 5750d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 5760d09e41aSPaolo Bonzini 57779853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 57879853e18STyrel Datwyler 5792b7dc949SPaolo Bonzini typedef struct sPAPRTCETable sPAPRTCETable; 5800d09e41aSPaolo Bonzini 581a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 582a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 583a83000f5SAnthony Liguori OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 584a83000f5SAnthony Liguori 585a83000f5SAnthony Liguori struct sPAPRTCETable { 586a83000f5SAnthony Liguori DeviceState parent; 587a83000f5SAnthony Liguori uint32_t liobn; 588a83000f5SAnthony Liguori uint32_t nb_table; 5891b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 590650f33adSAlexey Kardashevskiy uint32_t page_shift; 591a83000f5SAnthony Liguori uint64_t *table; 592a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 593a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 594a83000f5SAnthony Liguori bool bypass; 5956a81dd17SDavid Gibson bool need_vfio; 596a83000f5SAnthony Liguori int fd; 597b4b6eb77SAlexey Kardashevskiy MemoryRegion root, iommu; 598ee9a569aSAlexey Kardashevskiy struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 599a83000f5SAnthony Liguori QLIST_ENTRY(sPAPRTCETable) list; 600a83000f5SAnthony Liguori }; 601a83000f5SAnthony Liguori 602f9ce8e0aSThomas Huth sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 60331fe14d1SNathan Fontenot 60431fe14d1SNathan Fontenot struct sPAPREventLogEntry { 60531fe14d1SNathan Fontenot int log_type; 60631fe14d1SNathan Fontenot void *data; 60731fe14d1SNathan Fontenot QTAILQ_ENTRY(sPAPREventLogEntry) next; 60831fe14d1SNathan Fontenot }; 60931fe14d1SNathan Fontenot 61028e02042SDavid Gibson void spapr_events_init(sPAPRMachineState *sm); 611ffbb1705SMichael Roth void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 61228e02042SDavid Gibson int spapr_h_cas_compose_response(sPAPRMachineState *sm, 61303d196b7SBharata B Rao target_ulong addr, target_ulong size, 6146787d27bSMichael Roth sPAPROptionVector *ov5_updates); 615b4db5413SSuraj Jitindar Singh void close_htab_fd(sPAPRMachineState *spapr); 616b4db5413SSuraj Jitindar Singh void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 61706ec79e8SBharata B Rao void spapr_free_hpt(sPAPRMachineState *spapr); 618df7625d4SAlexey Kardashevskiy sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 619df7625d4SAlexey Kardashevskiy void spapr_tce_table_enable(sPAPRTCETable *tcet, 620df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 621df7625d4SAlexey Kardashevskiy uint32_t nb_table); 622a26fdf39SAlexey Kardashevskiy void spapr_tce_table_disable(sPAPRTCETable *tcet); 623c10325d6SDavid Gibson void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 624c10325d6SDavid Gibson 625a84bb436SPaolo Bonzini MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 6260d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 6270d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 6280d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 6292b7dc949SPaolo Bonzini sPAPRTCETable *tcet); 630eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 6317a36ae7aSBharata B Rao void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 6327a36ae7aSBharata B Rao void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 6337a36ae7aSBharata B Rao void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 6347a36ae7aSBharata B Rao uint32_t count); 6357a36ae7aSBharata B Rao void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 6367a36ae7aSBharata B Rao uint32_t count); 637afdbd403SBharata B Rao void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 638afdbd403SBharata B Rao uint32_t count, uint32_t index); 639afdbd403SBharata B Rao void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 640afdbd403SBharata B Rao uint32_t count, uint32_t index); 641*7843c0d6SDavid Gibson void spapr_cpu_parse_features(sPAPRMachineState *spapr); 642af81cf32SBharata B Rao void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 643af81cf32SBharata B Rao sPAPRMachineState *spapr); 64428df36a1SDavid Gibson 64531834723SDaniel Henrique Barboza /* CPU and LMB DRC release callbacks. */ 64631834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 64731834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 64831834723SDaniel Henrique Barboza 649147ff807SCédric Le Goater void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 650147ff807SCédric Le Goater int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 65128df36a1SDavid Gibson 652147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 6530d09e41aSPaolo Bonzini 6544d9392beSThomas Huth int spapr_rng_populate_dt(void *fdt); 6554d9392beSThomas Huth 656db4ef288SBharata B Rao #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 657db4ef288SBharata B Rao 6584a1c9cf0SBharata B Rao /* 6594a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 6604a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 6614a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 6624a1c9cf0SBharata B Rao */ 6634a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 6644a1c9cf0SBharata B Rao 6654a1c9cf0SBharata B Rao /* 1GB alignment for hotplug memory region */ 6664a1c9cf0SBharata B Rao #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 6674a1c9cf0SBharata B Rao 66803d196b7SBharata B Rao /* 66903d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 67003d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 67103d196b7SBharata B Rao */ 67203d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 67303d196b7SBharata B Rao 67403d196b7SBharata B Rao /* 675d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 676d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 67703d196b7SBharata B Rao */ 67803d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 679d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 680d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 68103d196b7SBharata B Rao 6821c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 6831c7ad77eSNicholas Piggin 6842a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 685