12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11db1015e9SEduardo Habkost #include "qom/object.h" 12ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 130d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 140fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 15fc8c745dSAlexey Kardashevskiy #include "hw/ppc/vof.h" 160d09e41aSPaolo Bonzini 17ce2918cbSDavid Gibson struct SpaprVioBus; 18ce2918cbSDavid Gibson struct SpaprPhbState; 19ce2918cbSDavid Gibson struct SpaprNvram; 200d8d6a24SThomas Huth 21ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 22ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 23ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 240d09e41aSPaolo Bonzini 254be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 261b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 274be21d56SDavid Gibson 28afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 29afd10a0fSBharata B Rao 30147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 31147ff807SCédric Le Goater 328063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 33147ff807SCédric Le Goater 34ce2918cbSDavid Gibson struct SpaprRtcState { 35147ff807SCédric Le Goater /*< private >*/ 36147ff807SCédric Le Goater DeviceState parent_obj; 37147ff807SCédric Le Goater int64_t ns_offset; 38147ff807SCédric Le Goater }; 39147ff807SCédric Le Goater 40ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 4128e02042SDavid Gibson 4228e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 43a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 44183930c0SDavid Gibson 4530f4b05bSDavid Gibson typedef enum { 4630f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 4730f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 4830f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 4930f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 50ce2918cbSDavid Gibson } SpaprResizeHpt; 5130f4b05bSDavid Gibson 52183930c0SDavid Gibson /** 5333face6bSDavid Gibson * Capabilities 5433face6bSDavid Gibson */ 5533face6bSDavid Gibson 56ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 574e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 5829386642SDavid Gibson /* Vector Scalar Extensions */ 594e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 602d1fb9bcSDavid Gibson /* Decimal Floating Point */ 614e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 628f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 638f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 6409114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 6509114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 664be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 674be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 682309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 692309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 70b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 71b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 72c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 73c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 748ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 758ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 768af7e1feSNicholas Piggin /* Implements PAPR FWNMI option */ 778af7e1feSNicholas Piggin #define SPAPR_CAP_FWNMI 0x0A 7882123b75SBharata B Rao /* Support H_RPT_INVALIDATE */ 7982123b75SBharata B Rao #define SPAPR_CAP_RPT_INVALIDATE 0x0B 804e5fe368SSuraj Jitindar Singh /* Num Caps */ 8182123b75SBharata B Rao #define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1) 824e5fe368SSuraj Jitindar Singh 834e5fe368SSuraj Jitindar Singh /* 844e5fe368SSuraj Jitindar Singh * Capability Values 854e5fe368SSuraj Jitindar Singh */ 864e5fe368SSuraj Jitindar Singh /* Bool Caps */ 874e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 884e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 89399b2896SSuraj Jitindar Singh 90c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 91399b2896SSuraj Jitindar Singh 92399b2896SSuraj Jitindar Singh /* Generic */ 936898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 946898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 956898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 96399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 97c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 98c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 99399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1002d1fb9bcSDavid Gibson 101b7573092SDaniel Henrique Barboza #define FDT_MAX_SIZE 0x200000 10291067db1SAlexey Kardashevskiy 1033a6e4ce6SDaniel Henrique Barboza /* Max number of GPUs per system */ 10430499fddSGreg Kurz #define NVGPU_MAX_NUM 6 10530499fddSGreg Kurz 1063a6e4ce6SDaniel Henrique Barboza /* Max number of NUMA nodes */ 1073a6e4ce6SDaniel Henrique Barboza #define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM) 1083a6e4ce6SDaniel Henrique Barboza 1093a6e4ce6SDaniel Henrique Barboza /* 1103a6e4ce6SDaniel Henrique Barboza * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 1113a6e4ce6SDaniel Henrique Barboza * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 1123a6e4ce6SDaniel Henrique Barboza * kernel source. It represents the amount of associativity domains 1133a6e4ce6SDaniel Henrique Barboza * for non-CPU resources. 1143a6e4ce6SDaniel Henrique Barboza * 1153a6e4ce6SDaniel Henrique Barboza * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 1163a6e4ce6SDaniel Henrique Barboza * array for any non-CPU resource. 1173a6e4ce6SDaniel Henrique Barboza */ 1183a6e4ce6SDaniel Henrique Barboza #define FORM1_DIST_REF_POINTS 4 1193a6e4ce6SDaniel Henrique Barboza #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 1203a6e4ce6SDaniel Henrique Barboza 121e0eb84d4SDaniel Henrique Barboza /* 122e0eb84d4SDaniel Henrique Barboza * FORM2 NUMA affinity has a single associativity domain, giving 123e0eb84d4SDaniel Henrique Barboza * us a assoc size of 2. 124e0eb84d4SDaniel Henrique Barboza */ 125e0eb84d4SDaniel Henrique Barboza #define FORM2_DIST_REF_POINTS 1 126e0eb84d4SDaniel Henrique Barboza #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 127e0eb84d4SDaniel Henrique Barboza 128ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 129ce2918cbSDavid Gibson struct SpaprCapabilities { 1304e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 13133face6bSDavid Gibson }; 13233face6bSDavid Gibson 13333face6bSDavid Gibson /** 134ce2918cbSDavid Gibson * SpaprMachineClass: 135183930c0SDavid Gibson */ 136ce2918cbSDavid Gibson struct SpaprMachineClass { 137183930c0SDavid Gibson /*< private >*/ 138183930c0SDavid Gibson MachineClass parent_class; 139183930c0SDavid Gibson 140183930c0SDavid Gibson /*< public >*/ 141224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 142962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 143fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 14457040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 14546f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 14682cffa2eSCédric Le Goater bool legacy_irq_allocation; 14754255c1fSDavid Gibson uint32_t nr_xirqs; 1480a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1493725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1506c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 15129cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 1521052ab67SDavid Gibson hwaddr rma_limit; /* clamp the RMA to this size */ 153a6030d7eSReza Arbab bool pre_5_1_assoc_refpoints; 15429bfe52aSDaniel Henrique Barboza bool pre_5_2_numa_associativity; 155e0eb84d4SDaniel Henrique Barboza bool pre_6_2_numa_affinity; 15682cffa2eSCédric Le Goater 157f5598c92SGreg Kurz bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 158daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 159daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 160ec132efaSAlexey Kardashevskiy unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 161ec132efaSAlexey Kardashevskiy hwaddr *nv2atsd, Error **errp); 162ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 163ce2918cbSDavid Gibson SpaprCapabilities default_caps; 164ce2918cbSDavid Gibson SpaprIrq *irq; 165183930c0SDavid Gibson }; 16628e02042SDavid Gibson 16781b205ceSAlexey Kardashevskiy #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 16881b205ceSAlexey Kardashevskiy 16981b205ceSAlexey Kardashevskiy #define TYPE_SPAPR_WDT "spapr-wdt" 17081b205ceSAlexey Kardashevskiy OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 17181b205ceSAlexey Kardashevskiy 17281b205ceSAlexey Kardashevskiy typedef struct SpaprWatchdog { 17381b205ceSAlexey Kardashevskiy /*< private >*/ 17481b205ceSAlexey Kardashevskiy DeviceState parent_obj; 17581b205ceSAlexey Kardashevskiy /*< public >*/ 17681b205ceSAlexey Kardashevskiy 17781b205ceSAlexey Kardashevskiy QEMUTimer timer; 17881b205ceSAlexey Kardashevskiy uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 17981b205ceSAlexey Kardashevskiy uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 18081b205ceSAlexey Kardashevskiy } SpaprWatchdog; 18181b205ceSAlexey Kardashevskiy 18228e02042SDavid Gibson /** 183ce2918cbSDavid Gibson * SpaprMachineState: 18428e02042SDavid Gibson */ 185ce2918cbSDavid Gibson struct SpaprMachineState { 18628e02042SDavid Gibson /*< private >*/ 18728e02042SDavid Gibson MachineState parent_obj; 18828e02042SDavid Gibson 189ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 190ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 191ce2918cbSDavid Gibson struct SpaprNvram *nvram; 192ce2918cbSDavid Gibson SpaprRtcState rtc; 1930d09e41aSPaolo Bonzini 194ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1950d09e41aSPaolo Bonzini void *htab; 1964be21d56SDavid Gibson uint32_t htab_shift; 197a40888baSAlexey Kardashevskiy uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 198ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1990b0b8310SDavid Gibson 2000d09e41aSPaolo Bonzini hwaddr rma_size; 201fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 202fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 203fea35ca4SAlexey Kardashevskiy void *fdt_blob; 204a19f7fb0SDavid Gibson long kernel_size; 205a19f7fb0SDavid Gibson bool kernel_le; 20687262806SAlexey Kardashevskiy uint64_t kernel_addr; 207a19f7fb0SDavid Gibson uint32_t initrd_base; 208a19f7fb0SDavid Gibson long initrd_size; 209fc8c745dSAlexey Kardashevskiy Vof *vof; 210880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 21198a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 212f73eb948SPaolo Bonzini bool want_stdout_path; 213fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 2140d09e41aSPaolo Bonzini 215120f738aSNicholas Piggin /* Nested HV support (TCG only) */ 216120f738aSNicholas Piggin uint64_t nested_ptcr; 217120f738aSNicholas Piggin 2180d09e41aSPaolo Bonzini Notifier epow_notifier; 219ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 220ffbb1705SMichael Roth bool use_hotplug_event_source; 221ce2918cbSDavid Gibson SpaprEventSource *event_sources; 2224be21d56SDavid Gibson 2237843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 224daa36379SDavid Gibson bool cas_pre_isa3_guest; 225ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 226ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 2277843c0d6SDavid Gibson uint32_t max_compat_pvr; 2287843c0d6SDavid Gibson 2294be21d56SDavid Gibson /* Migration state */ 2304be21d56SDavid Gibson int htab_save_index; 2314be21d56SDavid Gibson bool htab_first_pass; 232e68cb8b4SAlexey Kardashevskiy int htab_fd; 23346503c2bSMichael Roth 2340cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 2350cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 2360cffce56SDavid Gibson * occurs during the unplug process. */ 237ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 2380cffce56SDavid Gibson 2398af7e1feSNicholas Piggin /* State related to FWNMI option */ 2408af7e1feSNicholas Piggin 241edfdbf9cSNicholas Piggin /* System Reset and Machine Check Notification Routine addresses 2428af7e1feSNicholas Piggin * registered by "ibm,nmi-register" RTAS call. 2439ac703acSAravinda Prasad */ 244edfdbf9cSNicholas Piggin target_ulong fwnmi_system_reset_addr; 2458af7e1feSNicholas Piggin target_ulong fwnmi_machine_check_addr; 2468af7e1feSNicholas Piggin 2478af7e1feSNicholas Piggin /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 2488af7e1feSNicholas Piggin * set to -1 if a FWNMI machine check is not in progress, else is set to 2498af7e1feSNicholas Piggin * the CPU that was delivered the machine check, and is set back to -1 2508af7e1feSNicholas Piggin * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 2518af7e1feSNicholas Piggin * to synchronize other CPUs. 2528af7e1feSNicholas Piggin */ 2538af7e1feSNicholas Piggin int fwnmi_machine_check_interlock; 2548af7e1feSNicholas Piggin QemuCond fwnmi_machine_check_interlock_cond; 2559ac703acSAravinda Prasad 2563bf0844fSGreg Kurz /* Set by -boot */ 2573bf0844fSGreg Kurz char *boot_device; 2583bf0844fSGreg Kurz 25928e02042SDavid Gibson /*< public >*/ 26028e02042SDavid Gibson char *kvm_type; 26127461d69SPrasad J Pandit char *host_model; 26227461d69SPrasad J Pandit char *host_serial; 263852ad27eSCédric Le Goater 26482cffa2eSCédric Le Goater int32_t irq_map_nr; 26582cffa2eSCédric Le Goater unsigned long *irq_map; 266ce2918cbSDavid Gibson SpaprIrq *irq; 267872ff3deSCédric Le Goater qemu_irq *qirqs; 26881106dddSDavid Gibson SpaprInterruptController *active_intc; 26981106dddSDavid Gibson ICSState *ics; 27081106dddSDavid Gibson SpaprXive *xive; 27133face6bSDavid Gibson 2724e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 273ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 274ec132efaSAlexey Kardashevskiy 275ec132efaSAlexey Kardashevskiy unsigned gpu_numa_id; 2760fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 2772500fb42SAravinda Prasad 278a165ac67SDaniel Henrique Barboza uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 279e0eb84d4SDaniel Henrique Barboza uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 280f1aa45ffSDaniel Henrique Barboza 2812500fb42SAravinda Prasad Error *fwnmi_migration_blocker; 28281b205ceSAlexey Kardashevskiy 28381b205ceSAlexey Kardashevskiy SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 28428e02042SDavid Gibson }; 2850d09e41aSPaolo Bonzini 2860d09e41aSPaolo Bonzini #define H_SUCCESS 0 2870d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2880d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2890d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2900d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2910d09e41aSPaolo Bonzini #define H_PARTIAL 5 2920d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2930d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2940d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2950d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2960d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2970d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2980d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2990d09e41aSPaolo Bonzini is a good time to retry */ 3000d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 3010d09e41aSPaolo Bonzini is a good time to retry */ 3020d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 3030d09e41aSPaolo Bonzini is a good time to retry */ 3040d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 3050d09e41aSPaolo Bonzini is a good time to retry */ 3060d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 3070d09e41aSPaolo Bonzini is a good time to retry */ 3080d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 3090d09e41aSPaolo Bonzini is a good time to retry */ 3100d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 3110d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 3120d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 3130d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 3140d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 3150d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 3160d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 3170d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 3180d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 3190d09e41aSPaolo Bonzini #define H_NO_MEM -9 3200d09e41aSPaolo Bonzini #define H_AUTHORITY -10 3210d09e41aSPaolo Bonzini #define H_PERMISSION -11 3220d09e41aSPaolo Bonzini #define H_DROPPED -12 3230d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 3240d09e41aSPaolo Bonzini #define H_DEST_PARM -14 3250d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 3260d09e41aSPaolo Bonzini #define H_RESOURCE -16 3270d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 3280d09e41aSPaolo Bonzini #define H_RH_PARM -18 3290d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 3300d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 3310d09e41aSPaolo Bonzini #define H_EQ_PARM -21 3320d09e41aSPaolo Bonzini #define H_RT_PARM -22 3330d09e41aSPaolo Bonzini #define H_ST_PARM -23 3340d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 3350d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 3360d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 3370d09e41aSPaolo Bonzini #define H_MEM_PARM -28 3380d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 3390d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 3400d09e41aSPaolo Bonzini #define H_PORT_PARM -31 3410d09e41aSPaolo Bonzini #define H_MCG_PARM -32 3420d09e41aSPaolo Bonzini #define H_VL_PARM -33 3430d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 3440d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 3450d09e41aSPaolo Bonzini 3460d09e41aSPaolo Bonzini #define H_MASK_PARM -37 3470d09e41aSPaolo Bonzini #define H_MCG_FULL -38 3480d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 3490d09e41aSPaolo Bonzini #define H_P_COUNTER -40 3500d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 3510d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 3520d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 3530d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 3540d09e41aSPaolo Bonzini #define H_R_STATE -45 3550d09e41aSPaolo Bonzini #define H_RESCINDEND -46 35642561bf2SAnton Blanchard #define H_P2 -55 35742561bf2SAnton Blanchard #define H_P3 -56 35842561bf2SAnton Blanchard #define H_P4 -57 35942561bf2SAnton Blanchard #define H_P5 -58 36042561bf2SAnton Blanchard #define H_P6 -59 36142561bf2SAnton Blanchard #define H_P7 -60 36242561bf2SAnton Blanchard #define H_P8 -61 36342561bf2SAnton Blanchard #define H_P9 -62 36481b205ceSAlexey Kardashevskiy #define H_NOOP -63 365b5513584SShivaprasad G Bhat #define H_UNSUPPORTED -67 366b5fca656SShivaprasad G Bhat #define H_OVERLAP -68 36742561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 3680d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 3690d09e41aSPaolo Bonzini 3700d09e41aSPaolo Bonzini 3710d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 3720d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 3730d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 3740d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 3750d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 3760d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3770d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3780d09e41aSPaolo Bonzini */ 3790d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3800d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3810d09e41aSPaolo Bonzini 3820d09e41aSPaolo Bonzini /* Flags */ 3830d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3840d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3850d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3860d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3870d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3880d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3890d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3900d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3910d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3920d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3930d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3940d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3950d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3960d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3970d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3980d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3990d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 4000d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 4010d09e41aSPaolo Bonzini 402a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 403a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 404a7913d5eSRavi Bangoria #define H_SET_MODE_RESOURCE_SET_DAWR0 2 405a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 406a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 407a46622fdSAlexey Kardashevskiy 408a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 40942561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 41042561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 41142561bf2SAnton Blanchard 4120d09e41aSPaolo Bonzini /* VASI States */ 4130d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 4140d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 4150d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 4160d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 4170d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 4180d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 4190d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 4200d09e41aSPaolo Bonzini 4210d09e41aSPaolo Bonzini /* DABRX flags */ 4220d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 4230d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 4240d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 4250d09e41aSPaolo Bonzini 4268acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 4278acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 4288acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 4298acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 4308acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 4318acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 4328acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 4338acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 434c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 435399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 43617fd09c0SNicholas Piggin 4378acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 4388acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 4398acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 440399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 44117fd09c0SNicholas Piggin #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 44217fd09c0SNicholas Piggin #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 4438acc2ae5SSuraj Jitindar Singh 4440d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 4450d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 4460d09e41aSPaolo Bonzini 4470d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 4480d09e41aSPaolo Bonzini #define H_REMOVE 0x04 4490d09e41aSPaolo Bonzini #define H_ENTER 0x08 4500d09e41aSPaolo Bonzini #define H_READ 0x0c 4510d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 4520d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 4530d09e41aSPaolo Bonzini #define H_PROTECT 0x18 4540d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 4550d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 4560d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 4570d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 4580d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 4590d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 4600d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 4610d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 4620d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 4630d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 4640d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 4650d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 4660d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 4670d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 4680d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 4690d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 4700d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 4710d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 4720d09e41aSPaolo Bonzini #define H_EOI 0x64 4730d09e41aSPaolo Bonzini #define H_CPPR 0x68 4740d09e41aSPaolo Bonzini #define H_IPI 0x6c 4750d09e41aSPaolo Bonzini #define H_IPOLL 0x70 4760d09e41aSPaolo Bonzini #define H_XIRR 0x74 4770d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 4780d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 4790d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4800d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4810d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4820d09e41aSPaolo Bonzini #define H_PROD 0xE8 4830d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4840d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4850d09e41aSPaolo Bonzini #define H_PURR 0xF4 4860d09e41aSPaolo Bonzini #define H_PIC 0xF8 4870d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4880d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4890d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4900d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4910d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4920d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4930d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4940d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4950d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4960d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4970d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4980d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4990d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 5000d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 5010d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 5020d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 5030d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 5040d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 5050d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 5060d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 5070d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 5080d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 5090d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 5100d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 5110d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 5120d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 5130d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 5140d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 5150d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 5160d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 5170d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 5180d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 5190d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 5200d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 5210d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 5220d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 5230d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 5240d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 5250d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 5260d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 5270d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 5280d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 5290d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 5300d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 531c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 5320d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 5330d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 5340d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 5350d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 5360d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 5370d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 5380d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 5390d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 5400d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 5410d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 5420d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 5430d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 5440d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 5450d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 5460d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 5470d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 5480d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 5490d09e41aSPaolo Bonzini #define H_JOIN 0x298 5500d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 5510d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 5520d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 5530d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 5540d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 555c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 5565d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 5574d9392beSThomas Huth #define H_RANDOM 0x300 55842561bf2SAnton Blanchard #define H_SET_MODE 0x31C 55930f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 56030f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 561d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 562d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 563d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 5641c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 56523bcd5ebSCédric Le Goater 56623bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 56723bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 56823bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 56923bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 57023bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 57123bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 57223bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 57323bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 57423bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 57523bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 57623bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 577b5fca656SShivaprasad G Bhat #define H_SCM_READ_METADATA 0x3E4 578b5fca656SShivaprasad G Bhat #define H_SCM_WRITE_METADATA 0x3E8 579b5fca656SShivaprasad G Bhat #define H_SCM_BIND_MEM 0x3EC 580b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_MEM 0x3F0 581b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_ALL 0x3FC 58253d7d7e2SVaibhav Jain #define H_SCM_HEALTH 0x400 58382123b75SBharata B Rao #define H_RPT_INVALIDATE 0x448 584b5513584SShivaprasad G Bhat #define H_SCM_FLUSH 0x44C 58581b205ceSAlexey Kardashevskiy #define H_WATCHDOG 0x45C 58623bcd5ebSCédric Le Goater 58781b205ceSAlexey Kardashevskiy #define MAX_HCALL_OPCODE H_WATCHDOG 5880d09e41aSPaolo Bonzini 5890d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5900d09e41aSPaolo Bonzini * as well. 5910d09e41aSPaolo Bonzini * 5920d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 593498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 594498cd995SGreg Kurz * for "platform-specific" hcalls. 5950d09e41aSPaolo Bonzini */ 5960d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5970d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5980d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5992a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 6002a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 601fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 602fc8c745dSAlexey Kardashevskiy /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 603fc8c745dSAlexey Kardashevskiy #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 604120f738aSNicholas Piggin 605120f738aSNicholas Piggin /* Platform-specific hcalls used for nested HV KVM */ 606120f738aSNicholas Piggin #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 607120f738aSNicholas Piggin #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 608120f738aSNicholas Piggin #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 609120f738aSNicholas Piggin #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 610120f738aSNicholas Piggin 611120f738aSNicholas Piggin #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 6120d09e41aSPaolo Bonzini 6130fb6bd07SMichael Roth /* 6140fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 6150fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 6160fb6bd07SMichael Roth */ 6170fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 6180fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 6190fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 6200fb6bd07SMichael Roth 621120f738aSNicholas Piggin /* 622120f738aSNicholas Piggin * Register state for entering a nested guest with H_ENTER_NESTED. 623120f738aSNicholas Piggin * New member must be added at the end. 624120f738aSNicholas Piggin */ 625120f738aSNicholas Piggin struct kvmppc_hv_guest_state { 626120f738aSNicholas Piggin uint64_t version; /* version of this structure layout, must be first */ 627120f738aSNicholas Piggin uint32_t lpid; 628120f738aSNicholas Piggin uint32_t vcpu_token; 629120f738aSNicholas Piggin /* These registers are hypervisor privileged (at least for writing) */ 630120f738aSNicholas Piggin uint64_t lpcr; 631120f738aSNicholas Piggin uint64_t pcr; 632120f738aSNicholas Piggin uint64_t amor; 633120f738aSNicholas Piggin uint64_t dpdes; 634120f738aSNicholas Piggin uint64_t hfscr; 635120f738aSNicholas Piggin int64_t tb_offset; 636120f738aSNicholas Piggin uint64_t dawr0; 637120f738aSNicholas Piggin uint64_t dawrx0; 638120f738aSNicholas Piggin uint64_t ciabr; 639120f738aSNicholas Piggin uint64_t hdec_expiry; 640120f738aSNicholas Piggin uint64_t purr; 641120f738aSNicholas Piggin uint64_t spurr; 642120f738aSNicholas Piggin uint64_t ic; 643120f738aSNicholas Piggin uint64_t vtb; 644120f738aSNicholas Piggin uint64_t hdar; 645120f738aSNicholas Piggin uint64_t hdsisr; 646120f738aSNicholas Piggin uint64_t heir; 647120f738aSNicholas Piggin uint64_t asdr; 648120f738aSNicholas Piggin /* These are OS privileged but need to be set late in guest entry */ 649120f738aSNicholas Piggin uint64_t srr0; 650120f738aSNicholas Piggin uint64_t srr1; 651120f738aSNicholas Piggin uint64_t sprg[4]; 652120f738aSNicholas Piggin uint64_t pidr; 653120f738aSNicholas Piggin uint64_t cfar; 654120f738aSNicholas Piggin uint64_t ppr; 655120f738aSNicholas Piggin /* Version 1 ends here */ 656120f738aSNicholas Piggin uint64_t dawr1; 657120f738aSNicholas Piggin uint64_t dawrx1; 658120f738aSNicholas Piggin /* Version 2 ends here */ 659120f738aSNicholas Piggin }; 660120f738aSNicholas Piggin 661120f738aSNicholas Piggin /* Latest version of hv_guest_state structure */ 662120f738aSNicholas Piggin #define HV_GUEST_STATE_VERSION 2 663120f738aSNicholas Piggin 664120f738aSNicholas Piggin /* Linux 64-bit powerpc pt_regs struct, used by nested HV */ 665120f738aSNicholas Piggin struct kvmppc_pt_regs { 666120f738aSNicholas Piggin uint64_t gpr[32]; 667120f738aSNicholas Piggin uint64_t nip; 668120f738aSNicholas Piggin uint64_t msr; 669120f738aSNicholas Piggin uint64_t orig_gpr3; /* Used for restarting system calls */ 670120f738aSNicholas Piggin uint64_t ctr; 671120f738aSNicholas Piggin uint64_t link; 672120f738aSNicholas Piggin uint64_t xer; 673120f738aSNicholas Piggin uint64_t ccr; 674120f738aSNicholas Piggin uint64_t softe; /* Soft enabled/disabled */ 675120f738aSNicholas Piggin uint64_t trap; /* Reason for being here */ 676120f738aSNicholas Piggin uint64_t dar; /* Fault registers */ 677120f738aSNicholas Piggin uint64_t dsisr; /* on 4xx/Book-E used for ESR */ 678120f738aSNicholas Piggin uint64_t result; /* Result of a system call */ 679120f738aSNicholas Piggin }; 6800fb6bd07SMichael Roth 681ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 6822a6593cbSAlexey Kardashevskiy uint32_t version_id; 683ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 6842a6593cbSAlexey Kardashevskiy 6850d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 686aaf87c66SThomas Huth do { \ 687aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 688aaf87c66SThomas Huth } while (0) 6890d09e41aSPaolo Bonzini 690ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 6910d09e41aSPaolo Bonzini target_ulong opcode, 6920d09e41aSPaolo Bonzini target_ulong *args); 6930d09e41aSPaolo Bonzini 6940d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 6950d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 6960d09e41aSPaolo Bonzini target_ulong *args); 697120f738aSNicholas Piggin 698120f738aSNicholas Piggin void spapr_exit_nested(PowerPCCPU *cpu, int excp); 699120f738aSNicholas Piggin 700962104f0SLucas Mateus Castro (alqotel) target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 701962104f0SLucas Mateus Castro (alqotel) target_ulong shift); 702962104f0SLucas Mateus Castro (alqotel) target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 703962104f0SLucas Mateus Castro (alqotel) target_ulong flags, target_ulong shift); 704962104f0SLucas Mateus Castro (alqotel) bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 705962104f0SLucas Mateus Castro (alqotel) void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 7060d09e41aSPaolo Bonzini 70703ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 70803ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 70903ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 71003ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 71103ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 71203ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 71303ef074cSNicholas Piggin 714ee954280SGavin Shan /* ibm,set-eeh-option */ 715ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 716ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 717ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 718ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 719ee954280SGavin Shan 720ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 721ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 722ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 723ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 724ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 725ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 726ee954280SGavin Shan 727ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 728ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 729ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 730ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 731ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 732ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 733ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 734ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 735ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 736ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 737ee954280SGavin Shan 738ee954280SGavin Shan /* ibm,set-slot-reset */ 739ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 740ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 741ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 742ee954280SGavin Shan 743ee954280SGavin Shan /* ibm,slot-error-detail */ 744ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 745ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 746ee954280SGavin Shan 747a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 748a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 749a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 750a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 751a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 752a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 7533ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 7549d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 7553ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 756c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 757a64d325dSAlexey Kardashevskiy 758ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 759ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 760ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 761ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 762ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 763ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 764ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 765ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 766ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 7674c7daca3SAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_2M 0x100 768ae4de14cSAlexey Kardashevskiy 7693a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 7703a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 7713a3b8502SAlexey Kardashevskiy 7723a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 7733a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 7743a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 7753a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 7763a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 7773a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 7783a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 7793a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 7803a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 7813a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 7823a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 7833a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 7843a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 7853a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 7863a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 7873a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 7883a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 7893a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 7903a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 7913a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 7923a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 7933a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 7943a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 7953a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 7963a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 7973a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 7983a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 7993a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 8003a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 8013a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 8023a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 8033a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 804ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 805ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 806ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 807ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 808ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 809ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 810ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 811ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 812ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 813ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 81493eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 815f03496bcSAravinda Prasad #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 816f03496bcSAravinda Prasad #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 8173a3b8502SAlexey Kardashevskiy 818f03496bcSAravinda Prasad #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 8193a3b8502SAlexey Kardashevskiy 8203052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 8213b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 8223052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 823b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 8243052d951SSam bobroff 8258c8639dfSMike Day /* RTAS indicator/sensor types 8268c8639dfSMike Day * 8278c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 8288c8639dfSMike Day * 8298c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 8308c8639dfSMike Day */ 8318c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 8328c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 8338c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 8348c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 8358c8639dfSMike Day 8363052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 8373052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 8383052d951SSam bobroff */ 8393052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 8403052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 8413052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 8423052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 8433052d951SSam bobroff 8444fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 8454fe822e0SAlexey Kardashevskiy { 8464fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 8474fe822e0SAlexey Kardashevskiy } 8484fe822e0SAlexey Kardashevskiy 8490d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 8500d09e41aSPaolo Bonzini { 851*6b5cf264SBernhard Beschow return ldl_be_phys(&address_space_memory, 852*6b5cf264SBernhard Beschow ppc64_phys_to_real(phys + 4 * n)); 8530d09e41aSPaolo Bonzini } 8540d09e41aSPaolo Bonzini 855a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 856a14aa92bSGavin Shan { 857a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 858a14aa92bSGavin Shan } 859a14aa92bSGavin Shan 8600d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 8610d09e41aSPaolo Bonzini { 862ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 8630d09e41aSPaolo Bonzini } 8640d09e41aSPaolo Bonzini 865ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 866210b580bSAnthony Liguori uint32_t token, 8670d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 8680d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 8693a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 870ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 8710d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 8720d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 8733f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 874ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 8750d09e41aSPaolo Bonzini 8760d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 8770d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 8780d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 8790d09e41aSPaolo Bonzini 8800d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 8814290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 882c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 883c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 884d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 885c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 8860d09e41aSPaolo Bonzini 8877381c5d1SAlexey Kardashevskiy #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 8880d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 8890d09e41aSPaolo Bonzini 89081fe70e4SAravinda Prasad /* Offset from rtas-base where error log is placed */ 89181fe70e4SAravinda Prasad #define RTAS_ERROR_LOG_OFFSET 0x30 89281fe70e4SAravinda Prasad 89379853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 89479853e18STyrel Datwyler 895bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 896bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 897bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 898bb2d8ab6SGreg Kurz */ 8995c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 900bb2d8ab6SGreg Kurz { 901bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 902bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 903bb2d8ab6SGreg Kurz } 904bb2d8ab6SGreg Kurz 9050d09e41aSPaolo Bonzini 906a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 9078063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 908a83000f5SAnthony Liguori 9091221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 9108110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 9118110fa1dSEduardo Habkost TYPE_SPAPR_IOMMU_MEMORY_REGION) 9121221a474SAlexey Kardashevskiy 913ce2918cbSDavid Gibson struct SpaprTceTable { 914a83000f5SAnthony Liguori DeviceState parent; 915a83000f5SAnthony Liguori uint32_t liobn; 916a83000f5SAnthony Liguori uint32_t nb_table; 9171b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 918650f33adSAlexey Kardashevskiy uint32_t page_shift; 919a83000f5SAnthony Liguori uint64_t *table; 920a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 921a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 922a83000f5SAnthony Liguori bool bypass; 9236a81dd17SDavid Gibson bool need_vfio; 9245f366667SAlexey Kardashevskiy bool skipping_replay; 92531cc81f7SAlexey Kardashevskiy bool def_win; 926a83000f5SAnthony Liguori int fd; 9273df9d748SAlexey Kardashevskiy MemoryRegion root; 9283df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 929ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 930ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 931a83000f5SAnthony Liguori }; 932a83000f5SAnthony Liguori 933ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 93431fe14d1SNathan Fontenot 935ce2918cbSDavid Gibson struct SpaprEventLogEntry { 936fd38804bSDaniel Henrique Barboza uint32_t summary; 937fd38804bSDaniel Henrique Barboza uint32_t extended_length; 938fd38804bSDaniel Henrique Barboza void *extended_log; 939ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 94031fe14d1SNathan Fontenot }; 94131fe14d1SNathan Fontenot 9420c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 943ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 944ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 945ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 9468897ea5aSDavid Gibson void spapr_setup_hpt(SpaprMachineState *spapr); 947ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 948068479e1SFabiano Rosas void spapr_check_mmu_mode(bool guest_radix); 949ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 950ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 951df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 952df7625d4SAlexey Kardashevskiy uint32_t nb_table); 953ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 954ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 955c10325d6SDavid Gibson 956ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 9570d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 9580d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 9590d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 960ce2918cbSDavid Gibson SpaprTceTable *tcet); 961c4c81d7dSGreg Kurz void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 962ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 963ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 964ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 9657a36ae7aSBharata B Rao uint32_t count); 966ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 9677a36ae7aSBharata B Rao uint32_t count); 968ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 969afdbd403SBharata B Rao uint32_t count, uint32_t index); 970ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 971afdbd403SBharata B Rao uint32_t count, uint32_t index); 9720b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 973a4e3a7c0SGreg Kurz int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 974ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 975ad334d89SGreg Kurz void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 976eb7f80fdSDaniel Henrique Barboza void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 977ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 978a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 979a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 98081fe70e4SAravinda Prasad void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 98128df36a1SDavid Gibson 98262d38c9bSGreg Kurz /* DRC callbacks. */ 98331834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 984ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 985345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 98631834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 987ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 98862d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 989bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 990ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 991bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 99231834723SDaniel Henrique Barboza 993ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 994ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 99528df36a1SDavid Gibson 996147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 9970d09e41aSPaolo Bonzini 998e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 999db4ef288SBharata B Rao 10004a1c9cf0SBharata B Rao /* 10014a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 10024a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 10034a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 10044a1c9cf0SBharata B Rao */ 10054a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 10064a1c9cf0SBharata B Rao 1007ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 1008ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 10094a1c9cf0SBharata B Rao 101003d196b7SBharata B Rao /* 101103d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 101203d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 101303d196b7SBharata B Rao */ 101403d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 101503d196b7SBharata B Rao 101603d196b7SBharata B Rao /* 1017d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 1018d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 101903d196b7SBharata B Rao */ 102003d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 1021d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 1022d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 10230911a60cSLeonardo Bras #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 102403d196b7SBharata B Rao 10251c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 10261c7ad77eSNicholas Piggin 10270b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 10280b0b8310SDavid Gibson 102914bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 1030cfdc5274SGreg Kurz bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 10312e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 10322e886fb3SSam Bobroff 10334e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 10344e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 10354e5fe368SSuraj Jitindar Singh 103633face6bSDavid Gibson /* 103733face6bSDavid Gibson * Handling of optional capabilities 103833face6bSDavid Gibson */ 10394e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 10404e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 10414e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 10428f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 104309114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 10444be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 104564d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 1046b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 1047c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 10488ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 10499d953ce4SAravinda Prasad extern const VMStateDescription vmstate_spapr_cap_fwnmi; 105082123b75SBharata B Rao extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 105181b205ceSAlexey Kardashevskiy extern const VMStateDescription vmstate_spapr_wdt; 1052be85537dSDavid Gibson 1053ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 105433face6bSDavid Gibson { 10554e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 105633face6bSDavid Gibson } 105733face6bSDavid Gibson 1058ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 1059ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 1060ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 106140c2281cSMarkus Armbruster void spapr_caps_add_properties(SpaprMachineClass *smc); 1062ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 106333face6bSDavid Gibson 106435dce34fSGreg Kurz bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1065123eec65SDavid Gibson Error **errp); 1066db592b5bSCédric Le Goater /* 1067db592b5bSCédric Le Goater * XIVE definitions 1068db592b5bSCédric Le Goater */ 1069db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 1070db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1071db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1072123eec65SDavid Gibson 107300fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 107481fe70e4SAravinda Prasad hwaddr spapr_get_rtas_addr(void); 107573598c75SGreg Kurz bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1076fc8c745dSAlexey Kardashevskiy 107721bde1ecSAlexey Kardashevskiy void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1078fc8c745dSAlexey Kardashevskiy void spapr_vof_quiesce(MachineState *ms); 1079fc8c745dSAlexey Kardashevskiy bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1080fc8c745dSAlexey Kardashevskiy void *val, int vallen); 1081fc8c745dSAlexey Kardashevskiy target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1082fc8c745dSAlexey Kardashevskiy target_ulong opcode, target_ulong *args); 1083fc8c745dSAlexey Kardashevskiy target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1084fc8c745dSAlexey Kardashevskiy CPUState *cs, 1085fc8c745dSAlexey Kardashevskiy target_ulong ovec_addr); 1086fc8c745dSAlexey Kardashevskiy void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1087fc8c745dSAlexey Kardashevskiy 108881b205ceSAlexey Kardashevskiy /* H_WATCHDOG */ 108981b205ceSAlexey Kardashevskiy void spapr_watchdog_init(SpaprMachineState *spapr); 109081b205ceSAlexey Kardashevskiy 10912a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 1092