12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 120d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 130fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 140d09e41aSPaolo Bonzini 15ce2918cbSDavid Gibson struct SpaprVioBus; 16ce2918cbSDavid Gibson struct SpaprPhbState; 17ce2918cbSDavid Gibson struct SpaprNvram; 180d8d6a24SThomas Huth 19ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 21ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 220d09e41aSPaolo Bonzini 234be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 241b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 254be21d56SDavid Gibson 26afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 27afd10a0fSBharata B Rao 28147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 29147ff807SCédric Le Goater 30147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 31ce2918cbSDavid Gibson OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32147ff807SCédric Le Goater 33ce2918cbSDavid Gibson typedef struct SpaprRtcState SpaprRtcState; 34ce2918cbSDavid Gibson struct SpaprRtcState { 35147ff807SCédric Le Goater /*< private >*/ 36147ff807SCédric Le Goater DeviceState parent_obj; 37147ff807SCédric Le Goater int64_t ns_offset; 38147ff807SCédric Le Goater }; 39147ff807SCédric Le Goater 40ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 41ce2918cbSDavid Gibson typedef struct SpaprMachineClass SpaprMachineClass; 4228e02042SDavid Gibson 4328e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 4428e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 45ce2918cbSDavid Gibson OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 46183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 47ce2918cbSDavid Gibson OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 48183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 49ce2918cbSDavid Gibson OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 50183930c0SDavid Gibson 5130f4b05bSDavid Gibson typedef enum { 5230f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5430f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5530f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 56ce2918cbSDavid Gibson } SpaprResizeHpt; 5730f4b05bSDavid Gibson 58183930c0SDavid Gibson /** 5933face6bSDavid Gibson * Capabilities 6033face6bSDavid Gibson */ 6133face6bSDavid Gibson 62ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 634e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6429386642SDavid Gibson /* Vector Scalar Extensions */ 654e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 662d1fb9bcSDavid Gibson /* Decimal Floating Point */ 674e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 688f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 698f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 7009114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 7109114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 724be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 734be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 742309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 752309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 76b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 77b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 78c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 79c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 808ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 818ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 829d953ce4SAravinda Prasad /* FWNMI machine check handling */ 839d953ce4SAravinda Prasad #define SPAPR_CAP_FWNMI_MCE 0x0A 844e5fe368SSuraj Jitindar Singh /* Num Caps */ 859d953ce4SAravinda Prasad #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) 864e5fe368SSuraj Jitindar Singh 874e5fe368SSuraj Jitindar Singh /* 884e5fe368SSuraj Jitindar Singh * Capability Values 894e5fe368SSuraj Jitindar Singh */ 904e5fe368SSuraj Jitindar Singh /* Bool Caps */ 914e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 924e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 93399b2896SSuraj Jitindar Singh 94c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 95399b2896SSuraj Jitindar Singh 96399b2896SSuraj Jitindar Singh /* Generic */ 976898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 986898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 996898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 100399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 101c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 102c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 103399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1042d1fb9bcSDavid Gibson 105ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 106ce2918cbSDavid Gibson struct SpaprCapabilities { 1074e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 10833face6bSDavid Gibson }; 10933face6bSDavid Gibson 11033face6bSDavid Gibson /** 111ce2918cbSDavid Gibson * SpaprMachineClass: 112183930c0SDavid Gibson */ 113ce2918cbSDavid Gibson struct SpaprMachineClass { 114183930c0SDavid Gibson /*< private >*/ 115183930c0SDavid Gibson MachineClass parent_class; 116183930c0SDavid Gibson 117183930c0SDavid Gibson /*< public >*/ 118224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 119962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 120fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 12157040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 12246f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 12382cffa2eSCédric Le Goater bool legacy_irq_allocation; 12454255c1fSDavid Gibson uint32_t nr_xirqs; 1250a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1263725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1276c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 12829cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 1291052ab67SDavid Gibson hwaddr rma_limit; /* clamp the RMA to this size */ 13082cffa2eSCédric Le Goater 131ce2918cbSDavid Gibson void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 132daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 133daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 134ec132efaSAlexey Kardashevskiy unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 135ec132efaSAlexey Kardashevskiy hwaddr *nv2atsd, Error **errp); 136ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 137ce2918cbSDavid Gibson SpaprCapabilities default_caps; 138ce2918cbSDavid Gibson SpaprIrq *irq; 139183930c0SDavid Gibson }; 14028e02042SDavid Gibson 14128e02042SDavid Gibson /** 142ce2918cbSDavid Gibson * SpaprMachineState: 14328e02042SDavid Gibson */ 144ce2918cbSDavid Gibson struct SpaprMachineState { 14528e02042SDavid Gibson /*< private >*/ 14628e02042SDavid Gibson MachineState parent_obj; 14728e02042SDavid Gibson 148ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 149ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 150ce2918cbSDavid Gibson struct SpaprNvram *nvram; 151ce2918cbSDavid Gibson SpaprRtcState rtc; 1520d09e41aSPaolo Bonzini 153ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1540d09e41aSPaolo Bonzini void *htab; 1554be21d56SDavid Gibson uint32_t htab_shift; 1569861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 157ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1580b0b8310SDavid Gibson 1590d09e41aSPaolo Bonzini hwaddr rma_size; 160fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 161fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 162fea35ca4SAlexey Kardashevskiy void *fdt_blob; 163a19f7fb0SDavid Gibson long kernel_size; 164a19f7fb0SDavid Gibson bool kernel_le; 16587262806SAlexey Kardashevskiy uint64_t kernel_addr; 166a19f7fb0SDavid Gibson uint32_t initrd_base; 167a19f7fb0SDavid Gibson long initrd_size; 168880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 16998a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1700d09e41aSPaolo Bonzini bool has_graphics; 171fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1720d09e41aSPaolo Bonzini 1730d09e41aSPaolo Bonzini Notifier epow_notifier; 174ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 175ffbb1705SMichael Roth bool use_hotplug_event_source; 176ce2918cbSDavid Gibson SpaprEventSource *event_sources; 1774be21d56SDavid Gibson 1787843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 1797843c0d6SDavid Gibson bool cas_reboot; 180daa36379SDavid Gibson bool cas_pre_isa3_guest; 181ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 182ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1837843c0d6SDavid Gibson uint32_t max_compat_pvr; 1847843c0d6SDavid Gibson 1854be21d56SDavid Gibson /* Migration state */ 1864be21d56SDavid Gibson int htab_save_index; 1874be21d56SDavid Gibson bool htab_first_pass; 188e68cb8b4SAlexey Kardashevskiy int htab_fd; 18946503c2bSMichael Roth 1900cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1910cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1920cffce56SDavid Gibson * occurs during the unplug process. */ 193ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 1940cffce56SDavid Gibson 1959ac703acSAravinda Prasad /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ 1969ac703acSAravinda Prasad target_ulong guest_machine_check_addr; 1979ac703acSAravinda Prasad /* 1989ac703acSAravinda Prasad * mc_status is set to -1 if mc is not in progress, else is set to the CPU 1999ac703acSAravinda Prasad * handling the mc. 2009ac703acSAravinda Prasad */ 2019ac703acSAravinda Prasad int mc_status; 2029ac703acSAravinda Prasad QemuCond mc_delivery_cond; 2039ac703acSAravinda Prasad 20428e02042SDavid Gibson /*< public >*/ 20528e02042SDavid Gibson char *kvm_type; 20627461d69SPrasad J Pandit char *host_model; 20727461d69SPrasad J Pandit char *host_serial; 208852ad27eSCédric Le Goater 20982cffa2eSCédric Le Goater int32_t irq_map_nr; 21082cffa2eSCédric Le Goater unsigned long *irq_map; 211ce2918cbSDavid Gibson SpaprIrq *irq; 212872ff3deSCédric Le Goater qemu_irq *qirqs; 21381106dddSDavid Gibson SpaprInterruptController *active_intc; 21481106dddSDavid Gibson ICSState *ics; 21581106dddSDavid Gibson SpaprXive *xive; 21633face6bSDavid Gibson 2174e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 218ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 219ec132efaSAlexey Kardashevskiy 220ec132efaSAlexey Kardashevskiy unsigned gpu_numa_id; 2210fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 2222500fb42SAravinda Prasad 2232500fb42SAravinda Prasad Error *fwnmi_migration_blocker; 22428e02042SDavid Gibson }; 2250d09e41aSPaolo Bonzini 2260d09e41aSPaolo Bonzini #define H_SUCCESS 0 2270d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2280d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2290d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2300d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2310d09e41aSPaolo Bonzini #define H_PARTIAL 5 2320d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2330d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2340d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2350d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2360d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2370d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2380d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2390d09e41aSPaolo Bonzini is a good time to retry */ 2400d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2410d09e41aSPaolo Bonzini is a good time to retry */ 2420d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2430d09e41aSPaolo Bonzini is a good time to retry */ 2440d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2450d09e41aSPaolo Bonzini is a good time to retry */ 2460d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2470d09e41aSPaolo Bonzini is a good time to retry */ 2480d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2490d09e41aSPaolo Bonzini is a good time to retry */ 2500d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2510d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2520d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2530d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2540d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2550d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2560d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2570d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2580d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2590d09e41aSPaolo Bonzini #define H_NO_MEM -9 2600d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2610d09e41aSPaolo Bonzini #define H_PERMISSION -11 2620d09e41aSPaolo Bonzini #define H_DROPPED -12 2630d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2640d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2650d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2660d09e41aSPaolo Bonzini #define H_RESOURCE -16 2670d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2680d09e41aSPaolo Bonzini #define H_RH_PARM -18 2690d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2700d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2710d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2720d09e41aSPaolo Bonzini #define H_RT_PARM -22 2730d09e41aSPaolo Bonzini #define H_ST_PARM -23 2740d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 2750d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 2760d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 2770d09e41aSPaolo Bonzini #define H_MEM_PARM -28 2780d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 2790d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 2800d09e41aSPaolo Bonzini #define H_PORT_PARM -31 2810d09e41aSPaolo Bonzini #define H_MCG_PARM -32 2820d09e41aSPaolo Bonzini #define H_VL_PARM -33 2830d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 2840d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 2850d09e41aSPaolo Bonzini 2860d09e41aSPaolo Bonzini #define H_MASK_PARM -37 2870d09e41aSPaolo Bonzini #define H_MCG_FULL -38 2880d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 2890d09e41aSPaolo Bonzini #define H_P_COUNTER -40 2900d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 2910d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 2920d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 2930d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 2940d09e41aSPaolo Bonzini #define H_R_STATE -45 2950d09e41aSPaolo Bonzini #define H_RESCINDEND -46 29642561bf2SAnton Blanchard #define H_P2 -55 29742561bf2SAnton Blanchard #define H_P3 -56 29842561bf2SAnton Blanchard #define H_P4 -57 29942561bf2SAnton Blanchard #define H_P5 -58 30042561bf2SAnton Blanchard #define H_P6 -59 30142561bf2SAnton Blanchard #define H_P7 -60 30242561bf2SAnton Blanchard #define H_P8 -61 30342561bf2SAnton Blanchard #define H_P9 -62 304b5fca656SShivaprasad G Bhat #define H_OVERLAP -68 30542561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 3060d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 3070d09e41aSPaolo Bonzini 3080d09e41aSPaolo Bonzini 3090d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 3100d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 3110d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 3120d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 3130d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 3140d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3150d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3160d09e41aSPaolo Bonzini */ 3170d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3180d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3190d09e41aSPaolo Bonzini 3200d09e41aSPaolo Bonzini /* Flags */ 3210d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3220d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3230d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3240d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3250d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3260d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3270d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3280d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3290d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3300d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3310d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3320d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3330d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3340d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3350d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3360d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3370d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3380d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3390d09e41aSPaolo Bonzini 340a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 341a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 342a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 343a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 344a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 345a46622fdSAlexey Kardashevskiy 346a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 34742561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 34842561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 34942561bf2SAnton Blanchard 3500d09e41aSPaolo Bonzini /* VASI States */ 3510d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3520d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3530d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3540d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3550d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3560d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3570d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3580d09e41aSPaolo Bonzini 3590d09e41aSPaolo Bonzini /* DABRX flags */ 3600d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3610d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3620d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3630d09e41aSPaolo Bonzini 3648acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3658acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3668acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3678acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3688acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3698acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3708acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3718acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 372c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 373399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 3748acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 3758acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 3768acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 377399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 3788acc2ae5SSuraj Jitindar Singh 3790d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 3800d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 3810d09e41aSPaolo Bonzini 3820d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 3830d09e41aSPaolo Bonzini #define H_REMOVE 0x04 3840d09e41aSPaolo Bonzini #define H_ENTER 0x08 3850d09e41aSPaolo Bonzini #define H_READ 0x0c 3860d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 3870d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 3880d09e41aSPaolo Bonzini #define H_PROTECT 0x18 3890d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 3900d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 3910d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 3920d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 3930d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 3940d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 3950d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 3960d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 3970d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 3980d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 3990d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 4000d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 4010d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 4020d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 4030d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 4040d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 4050d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 4060d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 4070d09e41aSPaolo Bonzini #define H_EOI 0x64 4080d09e41aSPaolo Bonzini #define H_CPPR 0x68 4090d09e41aSPaolo Bonzini #define H_IPI 0x6c 4100d09e41aSPaolo Bonzini #define H_IPOLL 0x70 4110d09e41aSPaolo Bonzini #define H_XIRR 0x74 4120d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 4130d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 4140d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4150d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4160d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4170d09e41aSPaolo Bonzini #define H_PROD 0xE8 4180d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4190d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4200d09e41aSPaolo Bonzini #define H_PURR 0xF4 4210d09e41aSPaolo Bonzini #define H_PIC 0xF8 4220d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4230d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4240d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4250d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4260d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4270d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4280d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4290d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4300d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4310d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4320d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4330d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4340d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4350d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4360d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4370d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4380d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4390d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4400d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4410d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4420d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4430d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4440d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4450d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4460d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4470d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4480d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4490d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4500d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4510d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4520d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4530d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4540d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4550d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4560d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4570d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4580d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4590d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4600d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4610d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4620d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4630d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4640d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4650d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 466c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4670d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4680d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4690d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4700d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4710d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4720d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4730d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4740d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 4750d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 4760d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 4770d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 4780d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 4790d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 4800d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 4810d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 4820d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 4830d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 4840d09e41aSPaolo Bonzini #define H_JOIN 0x298 4850d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 4860d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 4870d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 4880d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 4890d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 490c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 4915d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 4924d9392beSThomas Huth #define H_RANDOM 0x300 49342561bf2SAnton Blanchard #define H_SET_MODE 0x31C 49430f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 49530f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 496d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 497d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 498d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 4991c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 50023bcd5ebSCédric Le Goater 50123bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 50223bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 50323bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 50423bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 50523bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 50623bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 50723bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 50823bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 50923bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 51023bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 51123bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 512b5fca656SShivaprasad G Bhat #define H_SCM_READ_METADATA 0x3E4 513b5fca656SShivaprasad G Bhat #define H_SCM_WRITE_METADATA 0x3E8 514b5fca656SShivaprasad G Bhat #define H_SCM_BIND_MEM 0x3EC 515b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_MEM 0x3F0 516b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_ALL 0x3FC 51723bcd5ebSCédric Le Goater 518b5fca656SShivaprasad G Bhat #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 5190d09e41aSPaolo Bonzini 5200d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5210d09e41aSPaolo Bonzini * as well. 5220d09e41aSPaolo Bonzini * 5230d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 524498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 525498cd995SGreg Kurz * for "platform-specific" hcalls. 5260d09e41aSPaolo Bonzini */ 5270d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5280d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5290d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5302a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5312a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 532fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 533fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 5340d09e41aSPaolo Bonzini 5350fb6bd07SMichael Roth /* 5360fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 5370fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 5380fb6bd07SMichael Roth */ 5390fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 5400fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 5410fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 5420fb6bd07SMichael Roth 5430fb6bd07SMichael Roth 544ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 5452a6593cbSAlexey Kardashevskiy uint32_t version_id; 546ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 5472a6593cbSAlexey Kardashevskiy 5480d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 549aaf87c66SThomas Huth do { \ 550aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 551aaf87c66SThomas Huth } while (0) 5520d09e41aSPaolo Bonzini 553ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 5540d09e41aSPaolo Bonzini target_ulong opcode, 5550d09e41aSPaolo Bonzini target_ulong *args); 5560d09e41aSPaolo Bonzini 5570d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5580d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5590d09e41aSPaolo Bonzini target_ulong *args); 5600d09e41aSPaolo Bonzini 56103ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 56203ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 56303ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 56403ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 56503ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 56603ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 56703ef074cSNicholas Piggin 568ee954280SGavin Shan /* ibm,set-eeh-option */ 569ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 570ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 571ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 572ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 573ee954280SGavin Shan 574ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 575ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 576ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 577ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 578ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 579ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 580ee954280SGavin Shan 581ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 582ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 583ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 584ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 585ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 586ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 587ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 588ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 589ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 590ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 591ee954280SGavin Shan 592ee954280SGavin Shan /* ibm,set-slot-reset */ 593ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 594ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 595ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 596ee954280SGavin Shan 597ee954280SGavin Shan /* ibm,slot-error-detail */ 598ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 599ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 600ee954280SGavin Shan 601a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 602a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 603a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 604a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 605a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 606a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 6073ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 6089d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 6093ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 610c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 611a64d325dSAlexey Kardashevskiy 612ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 613ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 614ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 615ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 616ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 617ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 618ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 619ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 620ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 621ae4de14cSAlexey Kardashevskiy 6223a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 6233a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 6243a3b8502SAlexey Kardashevskiy 6253a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 6263a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 6273a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 6283a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 6293a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 6303a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 6313a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 6323a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 6333a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 6343a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 6353a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 6363a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 6373a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 6383a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 6393a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 6403a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 6413a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 6423a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 6433a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 6443a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 6453a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 6463a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 6473a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 6483a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 6493a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 6503a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 6513a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 6523a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 6533a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 6543a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 6553a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6563a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 657ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 658ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 659ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 660ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 661ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 662ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 663ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 664ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 665ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 666ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 66793eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 668f03496bcSAravinda Prasad #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 669f03496bcSAravinda Prasad #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 6703a3b8502SAlexey Kardashevskiy 671f03496bcSAravinda Prasad #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 6723a3b8502SAlexey Kardashevskiy 6733052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 6743b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 6753052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 676b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 6773052d951SSam bobroff 6788c8639dfSMike Day /* RTAS indicator/sensor types 6798c8639dfSMike Day * 6808c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 6818c8639dfSMike Day * 6828c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 6838c8639dfSMike Day */ 6848c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 6858c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 6868c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 6878c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 6888c8639dfSMike Day 6893052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 6903052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 6913052d951SSam bobroff */ 6923052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 6933052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 6943052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 6953052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 6963052d951SSam bobroff 6974fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 6984fe822e0SAlexey Kardashevskiy { 6994fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 7004fe822e0SAlexey Kardashevskiy } 7014fe822e0SAlexey Kardashevskiy 7020d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 7030d09e41aSPaolo Bonzini { 704fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 7050d09e41aSPaolo Bonzini } 7060d09e41aSPaolo Bonzini 707a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 708a14aa92bSGavin Shan { 709a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 710a14aa92bSGavin Shan } 711a14aa92bSGavin Shan 7120d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 7130d09e41aSPaolo Bonzini { 714ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 7150d09e41aSPaolo Bonzini } 7160d09e41aSPaolo Bonzini 717ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 718210b580bSAnthony Liguori uint32_t token, 7190d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 7200d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7213a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 722ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 7230d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 7240d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7253f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 726ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 7270d09e41aSPaolo Bonzini 7280d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 7290d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 7300d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 7310d09e41aSPaolo Bonzini 7320d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 7334290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 734c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 735c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 736d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 737c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 7380d09e41aSPaolo Bonzini 739*4dba8722SAlexey Kardashevskiy #define RTAS_SIZE 2048 7400d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 7410d09e41aSPaolo Bonzini 74281fe70e4SAravinda Prasad /* Offset from rtas-base where error log is placed */ 74381fe70e4SAravinda Prasad #define RTAS_ERROR_LOG_OFFSET 0x30 74481fe70e4SAravinda Prasad 74579853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 74679853e18STyrel Datwyler 747bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 748bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 749bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 750bb2d8ab6SGreg Kurz */ 7515c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 752bb2d8ab6SGreg Kurz { 753bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 754bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 755bb2d8ab6SGreg Kurz } 756bb2d8ab6SGreg Kurz 757ce2918cbSDavid Gibson typedef struct SpaprTceTable SpaprTceTable; 7580d09e41aSPaolo Bonzini 759a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 760a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 761ce2918cbSDavid Gibson OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 762a83000f5SAnthony Liguori 7631221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 7641221a474SAlexey Kardashevskiy #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 7651221a474SAlexey Kardashevskiy OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 7661221a474SAlexey Kardashevskiy 767ce2918cbSDavid Gibson struct SpaprTceTable { 768a83000f5SAnthony Liguori DeviceState parent; 769a83000f5SAnthony Liguori uint32_t liobn; 770a83000f5SAnthony Liguori uint32_t nb_table; 7711b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 772650f33adSAlexey Kardashevskiy uint32_t page_shift; 773a83000f5SAnthony Liguori uint64_t *table; 774a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 775a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 776a83000f5SAnthony Liguori bool bypass; 7776a81dd17SDavid Gibson bool need_vfio; 7785f366667SAlexey Kardashevskiy bool skipping_replay; 779a83000f5SAnthony Liguori int fd; 7803df9d748SAlexey Kardashevskiy MemoryRegion root; 7813df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 782ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 783ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 784a83000f5SAnthony Liguori }; 785a83000f5SAnthony Liguori 786ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 78731fe14d1SNathan Fontenot 788ce2918cbSDavid Gibson struct SpaprEventLogEntry { 789fd38804bSDaniel Henrique Barboza uint32_t summary; 790fd38804bSDaniel Henrique Barboza uint32_t extended_length; 791fd38804bSDaniel Henrique Barboza void *extended_log; 792ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 79331fe14d1SNathan Fontenot }; 79431fe14d1SNathan Fontenot 7950c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 796ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 797ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 798ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 7998897ea5aSDavid Gibson void spapr_setup_hpt(SpaprMachineState *spapr); 800ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 801ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 802ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 803df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 804df7625d4SAlexey Kardashevskiy uint32_t nb_table); 805ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 806ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 807c10325d6SDavid Gibson 808ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 8090d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 8100d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 8110d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 812ce2918cbSDavid Gibson SpaprTceTable *tcet); 813eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 814ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 815ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 816ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 8177a36ae7aSBharata B Rao uint32_t count); 818ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 8197a36ae7aSBharata B Rao uint32_t count); 820ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 821afdbd403SBharata B Rao uint32_t count, uint32_t index); 822ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 823afdbd403SBharata B Rao uint32_t count, uint32_t index); 8240b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 825ce2918cbSDavid Gibson void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 8262772cf6bSDavid Gibson Error **errp); 827ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 828ad334d89SGreg Kurz void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 829ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 830a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 831a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 83281fe70e4SAravinda Prasad void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 83328df36a1SDavid Gibson 83462d38c9bSGreg Kurz /* DRC callbacks. */ 83531834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 836ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 837345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 83831834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 839ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 84062d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 841bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 842ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 843bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 84431834723SDaniel Henrique Barboza 845ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 846ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 84728df36a1SDavid Gibson 848147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 8490d09e41aSPaolo Bonzini 850e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 851db4ef288SBharata B Rao 8524a1c9cf0SBharata B Rao /* 8534a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 8544a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 8554a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 8564a1c9cf0SBharata B Rao */ 8574a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 8584a1c9cf0SBharata B Rao 859ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 860ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 8614a1c9cf0SBharata B Rao 86203d196b7SBharata B Rao /* 86303d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 86403d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 86503d196b7SBharata B Rao */ 86603d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 86703d196b7SBharata B Rao 86803d196b7SBharata B Rao /* 869d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 870d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 87103d196b7SBharata B Rao */ 87203d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 873d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 874d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 87503d196b7SBharata B Rao 8761c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 8771c7ad77eSNicholas Piggin 8780b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 8790b0b8310SDavid Gibson 88014bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 881648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 8822e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 8832e886fb3SSam Bobroff 8844e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 8854e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 8864e5fe368SSuraj Jitindar Singh 88733face6bSDavid Gibson /* 88833face6bSDavid Gibson * Handling of optional capabilities 88933face6bSDavid Gibson */ 8904e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 8914e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 8924e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 8938f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 89409114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 8954be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 89664d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 897b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 898c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 8998ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 9009d953ce4SAravinda Prasad extern const VMStateDescription vmstate_spapr_cap_fwnmi; 901be85537dSDavid Gibson 902ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 90333face6bSDavid Gibson { 9044e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 90533face6bSDavid Gibson } 90633face6bSDavid Gibson 907ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 908ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 909ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 910ce2918cbSDavid Gibson void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 911ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 91233face6bSDavid Gibson 913ce2918cbSDavid Gibson void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 914123eec65SDavid Gibson Error **errp); 915db592b5bSCédric Le Goater /* 916db592b5bSCédric Le Goater * XIVE definitions 917db592b5bSCédric Le Goater */ 918db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 919db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 920db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 921123eec65SDavid Gibson 92200fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 92381fe70e4SAravinda Prasad hwaddr spapr_get_rtas_addr(void); 9242a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 925