12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11db1015e9SEduardo Habkost #include "qom/object.h" 12ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 130d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 140fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 150d09e41aSPaolo Bonzini 16ce2918cbSDavid Gibson struct SpaprVioBus; 17ce2918cbSDavid Gibson struct SpaprPhbState; 18ce2918cbSDavid Gibson struct SpaprNvram; 190d8d6a24SThomas Huth 20ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 22ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 230d09e41aSPaolo Bonzini 2446d80a56SPhilippe Mathieu-Daudé typedef struct Vof Vof; 2546d80a56SPhilippe Mathieu-Daudé 264be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 271b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 284be21d56SDavid Gibson 29afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 30afd10a0fSBharata B Rao 31147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 32147ff807SCédric Le Goater 338063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 34147ff807SCédric Le Goater 35ce2918cbSDavid Gibson struct SpaprRtcState { 36147ff807SCédric Le Goater /*< private >*/ 37147ff807SCédric Le Goater DeviceState parent_obj; 38147ff807SCédric Le Goater int64_t ns_offset; 39147ff807SCédric Le Goater }; 40147ff807SCédric Le Goater 41ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 4228e02042SDavid Gibson 4328e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 44a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 45183930c0SDavid Gibson 4630f4b05bSDavid Gibson typedef enum { 4730f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 4830f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 4930f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5030f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 51ce2918cbSDavid Gibson } SpaprResizeHpt; 5230f4b05bSDavid Gibson 53183930c0SDavid Gibson /** 5433face6bSDavid Gibson * Capabilities 5533face6bSDavid Gibson */ 5633face6bSDavid Gibson 57ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 584e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 5929386642SDavid Gibson /* Vector Scalar Extensions */ 604e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 612d1fb9bcSDavid Gibson /* Decimal Floating Point */ 624e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 638f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 648f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 6509114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 6609114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 674be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 684be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 692309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 702309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 71b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 72b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 73c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 74c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 758ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 768ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 778af7e1feSNicholas Piggin /* Implements PAPR FWNMI option */ 788af7e1feSNicholas Piggin #define SPAPR_CAP_FWNMI 0x0A 7982123b75SBharata B Rao /* Support H_RPT_INVALIDATE */ 8082123b75SBharata B Rao #define SPAPR_CAP_RPT_INVALIDATE 0x0B 81ccc5a4c5SNicholas Piggin /* Support for AIL modes */ 82ccc5a4c5SNicholas Piggin #define SPAPR_CAP_AIL_MODE_3 0x0C 834e5fe368SSuraj Jitindar Singh /* Num Caps */ 84ccc5a4c5SNicholas Piggin #define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) 854e5fe368SSuraj Jitindar Singh 864e5fe368SSuraj Jitindar Singh /* 874e5fe368SSuraj Jitindar Singh * Capability Values 884e5fe368SSuraj Jitindar Singh */ 894e5fe368SSuraj Jitindar Singh /* Bool Caps */ 904e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 914e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 92399b2896SSuraj Jitindar Singh 93c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 94399b2896SSuraj Jitindar Singh 95399b2896SSuraj Jitindar Singh /* Generic */ 966898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 976898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 986898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 99399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 100c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 101c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 102399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1032d1fb9bcSDavid Gibson 104b7573092SDaniel Henrique Barboza #define FDT_MAX_SIZE 0x200000 10591067db1SAlexey Kardashevskiy 1063a6e4ce6SDaniel Henrique Barboza /* Max number of NUMA nodes */ 107*44fa20c9SCédric Le Goater #define NUMA_NODES_MAX_NUM (MAX_NODES) 1083a6e4ce6SDaniel Henrique Barboza 1093a6e4ce6SDaniel Henrique Barboza /* 1103a6e4ce6SDaniel Henrique Barboza * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 1113a6e4ce6SDaniel Henrique Barboza * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 1123a6e4ce6SDaniel Henrique Barboza * kernel source. It represents the amount of associativity domains 1133a6e4ce6SDaniel Henrique Barboza * for non-CPU resources. 1143a6e4ce6SDaniel Henrique Barboza * 1153a6e4ce6SDaniel Henrique Barboza * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 1163a6e4ce6SDaniel Henrique Barboza * array for any non-CPU resource. 1173a6e4ce6SDaniel Henrique Barboza */ 1183a6e4ce6SDaniel Henrique Barboza #define FORM1_DIST_REF_POINTS 4 1193a6e4ce6SDaniel Henrique Barboza #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 1203a6e4ce6SDaniel Henrique Barboza 121e0eb84d4SDaniel Henrique Barboza /* 122e0eb84d4SDaniel Henrique Barboza * FORM2 NUMA affinity has a single associativity domain, giving 123e0eb84d4SDaniel Henrique Barboza * us a assoc size of 2. 124e0eb84d4SDaniel Henrique Barboza */ 125e0eb84d4SDaniel Henrique Barboza #define FORM2_DIST_REF_POINTS 1 126e0eb84d4SDaniel Henrique Barboza #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 127e0eb84d4SDaniel Henrique Barboza 128ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 129ce2918cbSDavid Gibson struct SpaprCapabilities { 1304e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 13133face6bSDavid Gibson }; 13233face6bSDavid Gibson 13333face6bSDavid Gibson /** 134ce2918cbSDavid Gibson * SpaprMachineClass: 135183930c0SDavid Gibson */ 136ce2918cbSDavid Gibson struct SpaprMachineClass { 137183930c0SDavid Gibson /*< private >*/ 138183930c0SDavid Gibson MachineClass parent_class; 139183930c0SDavid Gibson 140183930c0SDavid Gibson /*< public >*/ 141224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 142962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 143fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 14457040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 14546f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 14682cffa2eSCédric Le Goater bool legacy_irq_allocation; 14754255c1fSDavid Gibson uint32_t nr_xirqs; 1480a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1493725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1506c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 15129cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 1521052ab67SDavid Gibson hwaddr rma_limit; /* clamp the RMA to this size */ 153a6030d7eSReza Arbab bool pre_5_1_assoc_refpoints; 15429bfe52aSDaniel Henrique Barboza bool pre_5_2_numa_associativity; 155e0eb84d4SDaniel Henrique Barboza bool pre_6_2_numa_affinity; 15682cffa2eSCédric Le Goater 157f5598c92SGreg Kurz bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 158daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 159daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 160*44fa20c9SCédric Le Goater unsigned n_dma, uint32_t *liobns, Error **errp); 161ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 162ce2918cbSDavid Gibson SpaprCapabilities default_caps; 163ce2918cbSDavid Gibson SpaprIrq *irq; 164183930c0SDavid Gibson }; 16528e02042SDavid Gibson 16681b205ceSAlexey Kardashevskiy #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 16781b205ceSAlexey Kardashevskiy 16881b205ceSAlexey Kardashevskiy #define TYPE_SPAPR_WDT "spapr-wdt" 16981b205ceSAlexey Kardashevskiy OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 17081b205ceSAlexey Kardashevskiy 17181b205ceSAlexey Kardashevskiy typedef struct SpaprWatchdog { 17281b205ceSAlexey Kardashevskiy /*< private >*/ 17381b205ceSAlexey Kardashevskiy DeviceState parent_obj; 17481b205ceSAlexey Kardashevskiy /*< public >*/ 17581b205ceSAlexey Kardashevskiy 17681b205ceSAlexey Kardashevskiy QEMUTimer timer; 17781b205ceSAlexey Kardashevskiy uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 17881b205ceSAlexey Kardashevskiy uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 17981b205ceSAlexey Kardashevskiy } SpaprWatchdog; 18081b205ceSAlexey Kardashevskiy 18128e02042SDavid Gibson /** 182ce2918cbSDavid Gibson * SpaprMachineState: 18328e02042SDavid Gibson */ 184ce2918cbSDavid Gibson struct SpaprMachineState { 18528e02042SDavid Gibson /*< private >*/ 18628e02042SDavid Gibson MachineState parent_obj; 18728e02042SDavid Gibson 188ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 189ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 190ce2918cbSDavid Gibson struct SpaprNvram *nvram; 191ce2918cbSDavid Gibson SpaprRtcState rtc; 1920d09e41aSPaolo Bonzini 193ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1940d09e41aSPaolo Bonzini void *htab; 1954be21d56SDavid Gibson uint32_t htab_shift; 196a40888baSAlexey Kardashevskiy uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 197ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1980b0b8310SDavid Gibson 1990d09e41aSPaolo Bonzini hwaddr rma_size; 200fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 201fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 202fea35ca4SAlexey Kardashevskiy void *fdt_blob; 203b27fcb28SNicholas Piggin uint8_t fdt_rng_seed[32]; 204a19f7fb0SDavid Gibson long kernel_size; 205a19f7fb0SDavid Gibson bool kernel_le; 20687262806SAlexey Kardashevskiy uint64_t kernel_addr; 207a19f7fb0SDavid Gibson uint32_t initrd_base; 208a19f7fb0SDavid Gibson long initrd_size; 209fc8c745dSAlexey Kardashevskiy Vof *vof; 210880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 21198a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 212f73eb948SPaolo Bonzini bool want_stdout_path; 213fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 2140d09e41aSPaolo Bonzini 215120f738aSNicholas Piggin /* Nested HV support (TCG only) */ 216120f738aSNicholas Piggin uint64_t nested_ptcr; 217120f738aSNicholas Piggin 2180d09e41aSPaolo Bonzini Notifier epow_notifier; 219ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 220ffbb1705SMichael Roth bool use_hotplug_event_source; 221ce2918cbSDavid Gibson SpaprEventSource *event_sources; 2224be21d56SDavid Gibson 2237843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 224daa36379SDavid Gibson bool cas_pre_isa3_guest; 225ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 226ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 2277843c0d6SDavid Gibson uint32_t max_compat_pvr; 2287843c0d6SDavid Gibson 2294be21d56SDavid Gibson /* Migration state */ 2304be21d56SDavid Gibson int htab_save_index; 2314be21d56SDavid Gibson bool htab_first_pass; 232e68cb8b4SAlexey Kardashevskiy int htab_fd; 23346503c2bSMichael Roth 2340cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 2350cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 2360cffce56SDavid Gibson * occurs during the unplug process. */ 237ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 2380cffce56SDavid Gibson 2398af7e1feSNicholas Piggin /* State related to FWNMI option */ 2408af7e1feSNicholas Piggin 241edfdbf9cSNicholas Piggin /* System Reset and Machine Check Notification Routine addresses 2428af7e1feSNicholas Piggin * registered by "ibm,nmi-register" RTAS call. 2439ac703acSAravinda Prasad */ 244edfdbf9cSNicholas Piggin target_ulong fwnmi_system_reset_addr; 2458af7e1feSNicholas Piggin target_ulong fwnmi_machine_check_addr; 2468af7e1feSNicholas Piggin 2478af7e1feSNicholas Piggin /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 2488af7e1feSNicholas Piggin * set to -1 if a FWNMI machine check is not in progress, else is set to 2498af7e1feSNicholas Piggin * the CPU that was delivered the machine check, and is set back to -1 2508af7e1feSNicholas Piggin * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 2518af7e1feSNicholas Piggin * to synchronize other CPUs. 2528af7e1feSNicholas Piggin */ 2538af7e1feSNicholas Piggin int fwnmi_machine_check_interlock; 2548af7e1feSNicholas Piggin QemuCond fwnmi_machine_check_interlock_cond; 2559ac703acSAravinda Prasad 2563bf0844fSGreg Kurz /* Set by -boot */ 2573bf0844fSGreg Kurz char *boot_device; 2583bf0844fSGreg Kurz 25928e02042SDavid Gibson /*< public >*/ 26028e02042SDavid Gibson char *kvm_type; 26127461d69SPrasad J Pandit char *host_model; 26227461d69SPrasad J Pandit char *host_serial; 263852ad27eSCédric Le Goater 26482cffa2eSCédric Le Goater int32_t irq_map_nr; 26582cffa2eSCédric Le Goater unsigned long *irq_map; 266ce2918cbSDavid Gibson SpaprIrq *irq; 267872ff3deSCédric Le Goater qemu_irq *qirqs; 26881106dddSDavid Gibson SpaprInterruptController *active_intc; 26981106dddSDavid Gibson ICSState *ics; 27081106dddSDavid Gibson SpaprXive *xive; 27133face6bSDavid Gibson 2724e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 273ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 274ec132efaSAlexey Kardashevskiy 2750fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 2762500fb42SAravinda Prasad 277a165ac67SDaniel Henrique Barboza uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 278e0eb84d4SDaniel Henrique Barboza uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 279f1aa45ffSDaniel Henrique Barboza 2802500fb42SAravinda Prasad Error *fwnmi_migration_blocker; 28181b205ceSAlexey Kardashevskiy 28281b205ceSAlexey Kardashevskiy SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 28328e02042SDavid Gibson }; 2840d09e41aSPaolo Bonzini 2850d09e41aSPaolo Bonzini #define H_SUCCESS 0 2860d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2870d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2880d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2890d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2900d09e41aSPaolo Bonzini #define H_PARTIAL 5 2910d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2920d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2930d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2940d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2950d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2960d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2970d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2980d09e41aSPaolo Bonzini is a good time to retry */ 2990d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 3000d09e41aSPaolo Bonzini is a good time to retry */ 3010d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 3020d09e41aSPaolo Bonzini is a good time to retry */ 3030d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 3040d09e41aSPaolo Bonzini is a good time to retry */ 3050d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 3060d09e41aSPaolo Bonzini is a good time to retry */ 3070d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 3080d09e41aSPaolo Bonzini is a good time to retry */ 3090d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 3100d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 3110d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 3120d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 3130d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 3140d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 3150d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 3160d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 3170d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 3180d09e41aSPaolo Bonzini #define H_NO_MEM -9 3190d09e41aSPaolo Bonzini #define H_AUTHORITY -10 3200d09e41aSPaolo Bonzini #define H_PERMISSION -11 3210d09e41aSPaolo Bonzini #define H_DROPPED -12 3220d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 3230d09e41aSPaolo Bonzini #define H_DEST_PARM -14 3240d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 3250d09e41aSPaolo Bonzini #define H_RESOURCE -16 3260d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 3270d09e41aSPaolo Bonzini #define H_RH_PARM -18 3280d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 3290d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 3300d09e41aSPaolo Bonzini #define H_EQ_PARM -21 3310d09e41aSPaolo Bonzini #define H_RT_PARM -22 3320d09e41aSPaolo Bonzini #define H_ST_PARM -23 3330d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 3340d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 3350d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 3360d09e41aSPaolo Bonzini #define H_MEM_PARM -28 3370d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 3380d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 3390d09e41aSPaolo Bonzini #define H_PORT_PARM -31 3400d09e41aSPaolo Bonzini #define H_MCG_PARM -32 3410d09e41aSPaolo Bonzini #define H_VL_PARM -33 3420d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 3430d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 3440d09e41aSPaolo Bonzini 3450d09e41aSPaolo Bonzini #define H_MASK_PARM -37 3460d09e41aSPaolo Bonzini #define H_MCG_FULL -38 3470d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 3480d09e41aSPaolo Bonzini #define H_P_COUNTER -40 3490d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 3500d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 3510d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 3520d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 3530d09e41aSPaolo Bonzini #define H_R_STATE -45 3540d09e41aSPaolo Bonzini #define H_RESCINDEND -46 35542561bf2SAnton Blanchard #define H_P2 -55 35642561bf2SAnton Blanchard #define H_P3 -56 35742561bf2SAnton Blanchard #define H_P4 -57 35842561bf2SAnton Blanchard #define H_P5 -58 35942561bf2SAnton Blanchard #define H_P6 -59 36042561bf2SAnton Blanchard #define H_P7 -60 36142561bf2SAnton Blanchard #define H_P8 -61 36242561bf2SAnton Blanchard #define H_P9 -62 36381b205ceSAlexey Kardashevskiy #define H_NOOP -63 364b5513584SShivaprasad G Bhat #define H_UNSUPPORTED -67 365b5fca656SShivaprasad G Bhat #define H_OVERLAP -68 36642561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 3670d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 3680d09e41aSPaolo Bonzini 3690d09e41aSPaolo Bonzini 3700d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 3710d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 3720d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 3730d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 3740d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 3750d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3760d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3770d09e41aSPaolo Bonzini */ 3780d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3790d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3800d09e41aSPaolo Bonzini 3810d09e41aSPaolo Bonzini /* Flags */ 3820d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3830d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3840d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3850d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3860d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3870d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3880d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3890d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3900d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3910d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3920d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3930d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3940d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3950d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3960d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3970d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3980d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3990d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 4000d09e41aSPaolo Bonzini 401a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 402a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 403a7913d5eSRavi Bangoria #define H_SET_MODE_RESOURCE_SET_DAWR0 2 404a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 405a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 406a46622fdSAlexey Kardashevskiy 407a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 40842561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 40942561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 41042561bf2SAnton Blanchard 4110d09e41aSPaolo Bonzini /* VASI States */ 4120d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 4130d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 4140d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 4150d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 4160d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 4170d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 4180d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 4190d09e41aSPaolo Bonzini 4200d09e41aSPaolo Bonzini /* DABRX flags */ 4210d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 4220d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 4230d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 4240d09e41aSPaolo Bonzini 4258acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 4268acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 4278acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 4288acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 4298acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 4308acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 4318acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 4328acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 433c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 434399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 43517fd09c0SNicholas Piggin 4368acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 4378acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 4388acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 439399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 44017fd09c0SNicholas Piggin #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 44117fd09c0SNicholas Piggin #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 4428acc2ae5SSuraj Jitindar Singh 4430d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 4440d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 4450d09e41aSPaolo Bonzini 4460d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 4470d09e41aSPaolo Bonzini #define H_REMOVE 0x04 4480d09e41aSPaolo Bonzini #define H_ENTER 0x08 4490d09e41aSPaolo Bonzini #define H_READ 0x0c 4500d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 4510d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 4520d09e41aSPaolo Bonzini #define H_PROTECT 0x18 4530d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 4540d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 4550d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 4560d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 4570d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 4580d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 4590d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 4600d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 4610d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 4620d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 4630d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 4640d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 4650d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 4660d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 4670d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 4680d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 4690d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 4700d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 4710d09e41aSPaolo Bonzini #define H_EOI 0x64 4720d09e41aSPaolo Bonzini #define H_CPPR 0x68 4730d09e41aSPaolo Bonzini #define H_IPI 0x6c 4740d09e41aSPaolo Bonzini #define H_IPOLL 0x70 4750d09e41aSPaolo Bonzini #define H_XIRR 0x74 4760d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 4770d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 4780d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4790d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4800d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4810d09e41aSPaolo Bonzini #define H_PROD 0xE8 4820d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4830d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4840d09e41aSPaolo Bonzini #define H_PURR 0xF4 4850d09e41aSPaolo Bonzini #define H_PIC 0xF8 4860d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4870d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4880d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4890d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4900d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4910d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4920d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4930d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4940d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4950d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4960d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4970d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4980d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4990d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 5000d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 5010d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 5020d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 5030d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 5040d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 5050d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 5060d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 5070d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 5080d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 5090d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 5100d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 5110d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 5120d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 5130d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 5140d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 5150d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 5160d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 5170d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 5180d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 5190d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 5200d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 5210d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 5220d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 5230d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 5240d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 5250d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 5260d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 5270d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 5280d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 5290d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 530c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 5310d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 5320d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 5330d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 5340d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 5350d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 5360d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 5370d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 5380d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 5390d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 5400d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 5410d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 5420d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 5430d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 5440d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 5450d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 5460d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 5470d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 5480d09e41aSPaolo Bonzini #define H_JOIN 0x298 5490d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 5500d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 5510d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 5520d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 5530d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 554c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 5555d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 5564d9392beSThomas Huth #define H_RANDOM 0x300 55742561bf2SAnton Blanchard #define H_SET_MODE 0x31C 55830f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 55930f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 560d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 561d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 562d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 5631c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 56423bcd5ebSCédric Le Goater 56523bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 56623bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 56723bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 56823bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 56923bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 57023bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 57123bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 57223bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 57323bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 57423bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 57523bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 576b5fca656SShivaprasad G Bhat #define H_SCM_READ_METADATA 0x3E4 577b5fca656SShivaprasad G Bhat #define H_SCM_WRITE_METADATA 0x3E8 578b5fca656SShivaprasad G Bhat #define H_SCM_BIND_MEM 0x3EC 579b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_MEM 0x3F0 580b5fca656SShivaprasad G Bhat #define H_SCM_UNBIND_ALL 0x3FC 58153d7d7e2SVaibhav Jain #define H_SCM_HEALTH 0x400 58282123b75SBharata B Rao #define H_RPT_INVALIDATE 0x448 583b5513584SShivaprasad G Bhat #define H_SCM_FLUSH 0x44C 58481b205ceSAlexey Kardashevskiy #define H_WATCHDOG 0x45C 58523bcd5ebSCédric Le Goater 58681b205ceSAlexey Kardashevskiy #define MAX_HCALL_OPCODE H_WATCHDOG 5870d09e41aSPaolo Bonzini 5880d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5890d09e41aSPaolo Bonzini * as well. 5900d09e41aSPaolo Bonzini * 5910d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 592498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 593498cd995SGreg Kurz * for "platform-specific" hcalls. 5940d09e41aSPaolo Bonzini */ 5950d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5960d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5970d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5982a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5992a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 600fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 601fc8c745dSAlexey Kardashevskiy /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 602fc8c745dSAlexey Kardashevskiy #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 603120f738aSNicholas Piggin 604120f738aSNicholas Piggin /* Platform-specific hcalls used for nested HV KVM */ 605120f738aSNicholas Piggin #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 606120f738aSNicholas Piggin #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 607120f738aSNicholas Piggin #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 608120f738aSNicholas Piggin #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 609120f738aSNicholas Piggin 610120f738aSNicholas Piggin #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 6110d09e41aSPaolo Bonzini 6120fb6bd07SMichael Roth /* 6130fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 6140fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 6150fb6bd07SMichael Roth */ 6160fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 6170fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 6180fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 6190fb6bd07SMichael Roth 620ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 6212a6593cbSAlexey Kardashevskiy uint32_t version_id; 622ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 6232a6593cbSAlexey Kardashevskiy 6240d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 625aaf87c66SThomas Huth do { \ 626aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 627aaf87c66SThomas Huth } while (0) 6280d09e41aSPaolo Bonzini 629ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 6300d09e41aSPaolo Bonzini target_ulong opcode, 6310d09e41aSPaolo Bonzini target_ulong *args); 6320d09e41aSPaolo Bonzini 6330d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 6340d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 6350d09e41aSPaolo Bonzini target_ulong *args); 636120f738aSNicholas Piggin 637962104f0SLucas Mateus Castro (alqotel) target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 638962104f0SLucas Mateus Castro (alqotel) target_ulong shift); 639962104f0SLucas Mateus Castro (alqotel) target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 640962104f0SLucas Mateus Castro (alqotel) target_ulong flags, target_ulong shift); 641962104f0SLucas Mateus Castro (alqotel) bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 642962104f0SLucas Mateus Castro (alqotel) void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 6430d09e41aSPaolo Bonzini 64403ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 64503ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 64603ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 64703ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 64803ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 64903ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 65003ef074cSNicholas Piggin 651ee954280SGavin Shan /* ibm,set-eeh-option */ 652ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 653ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 654ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 655ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 656ee954280SGavin Shan 657ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 658ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 659ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 660ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 661ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 662ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 663ee954280SGavin Shan 664ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 665ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 666ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 667ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 668ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 669ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 670ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 671ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 672ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 673ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 674ee954280SGavin Shan 675ee954280SGavin Shan /* ibm,set-slot-reset */ 676ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 677ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 678ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 679ee954280SGavin Shan 680ee954280SGavin Shan /* ibm,slot-error-detail */ 681ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 682ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 683ee954280SGavin Shan 684a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 685a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 686a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 687a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 688a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 689a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 6903ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 6919d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 6923ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 693c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 694a64d325dSAlexey Kardashevskiy 695ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 696ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 697ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 698ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 699ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 700ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 701ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 702ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 703ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 7044c7daca3SAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_2M 0x100 705ae4de14cSAlexey Kardashevskiy 7063a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 7073a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 7083a3b8502SAlexey Kardashevskiy 7093a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 7103a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 7113a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 7123a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 7133a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 7143a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 7153a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 7163a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 7173a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 7183a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 7193a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 7203a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 7213a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 7223a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 7233a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 7243a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 7253a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 7263a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 7273a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 7283a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 7293a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 7303a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 7313a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 7323a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 7333a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 7343a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 7353a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 7363a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 7373a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 7383a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 7393a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 7403a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 741ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 742ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 743ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 744ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 745ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 746ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 747ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 748ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 749ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 750ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 75193eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 752f03496bcSAravinda Prasad #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 753f03496bcSAravinda Prasad #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 7543a3b8502SAlexey Kardashevskiy 755f03496bcSAravinda Prasad #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 7563a3b8502SAlexey Kardashevskiy 7573052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 7583b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 7593052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 760b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 7613052d951SSam bobroff 7628c8639dfSMike Day /* RTAS indicator/sensor types 7638c8639dfSMike Day * 7648c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 7658c8639dfSMike Day * 7668c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 7678c8639dfSMike Day */ 7688c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 7698c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 7708c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 7718c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 7728c8639dfSMike Day 7733052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 7743052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 7753052d951SSam bobroff */ 7763052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 7773052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 7783052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 7793052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 7803052d951SSam bobroff 7814fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 7824fe822e0SAlexey Kardashevskiy { 7834fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 7844fe822e0SAlexey Kardashevskiy } 7854fe822e0SAlexey Kardashevskiy 7860d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 7870d09e41aSPaolo Bonzini { 7886b5cf264SBernhard Beschow return ldl_be_phys(&address_space_memory, 7896b5cf264SBernhard Beschow ppc64_phys_to_real(phys + 4 * n)); 7900d09e41aSPaolo Bonzini } 7910d09e41aSPaolo Bonzini 792a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 793a14aa92bSGavin Shan { 794a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 795a14aa92bSGavin Shan } 796a14aa92bSGavin Shan 7970d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 7980d09e41aSPaolo Bonzini { 799ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 8000d09e41aSPaolo Bonzini } 8010d09e41aSPaolo Bonzini 802ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 803210b580bSAnthony Liguori uint32_t token, 8040d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 8050d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 8063a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 807ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 8080d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 8090d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 8103f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 811ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 8120d09e41aSPaolo Bonzini 8130d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 8140d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 8150d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 8160d09e41aSPaolo Bonzini 8170d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 8184290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 819c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 820c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 821d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 822c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 8230d09e41aSPaolo Bonzini 8247381c5d1SAlexey Kardashevskiy #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 8250d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 8260d09e41aSPaolo Bonzini 82781fe70e4SAravinda Prasad /* Offset from rtas-base where error log is placed */ 82881fe70e4SAravinda Prasad #define RTAS_ERROR_LOG_OFFSET 0x30 82981fe70e4SAravinda Prasad 83079853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 83179853e18STyrel Datwyler 832bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 833bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 834bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 835bb2d8ab6SGreg Kurz */ 8365c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 837bb2d8ab6SGreg Kurz { 838bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 839bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 840bb2d8ab6SGreg Kurz } 841bb2d8ab6SGreg Kurz 8420d09e41aSPaolo Bonzini 843a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 8448063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 845a83000f5SAnthony Liguori 8461221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 8478110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 8488110fa1dSEduardo Habkost TYPE_SPAPR_IOMMU_MEMORY_REGION) 8491221a474SAlexey Kardashevskiy 850ce2918cbSDavid Gibson struct SpaprTceTable { 851a83000f5SAnthony Liguori DeviceState parent; 852a83000f5SAnthony Liguori uint32_t liobn; 853a83000f5SAnthony Liguori uint32_t nb_table; 8541b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 855650f33adSAlexey Kardashevskiy uint32_t page_shift; 856a83000f5SAnthony Liguori uint64_t *table; 857a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 858a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 859a83000f5SAnthony Liguori bool bypass; 8606a81dd17SDavid Gibson bool need_vfio; 8615f366667SAlexey Kardashevskiy bool skipping_replay; 86231cc81f7SAlexey Kardashevskiy bool def_win; 863a83000f5SAnthony Liguori int fd; 8643df9d748SAlexey Kardashevskiy MemoryRegion root; 8653df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 866ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 867ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 868a83000f5SAnthony Liguori }; 869a83000f5SAnthony Liguori 870ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 87131fe14d1SNathan Fontenot 872ce2918cbSDavid Gibson struct SpaprEventLogEntry { 873fd38804bSDaniel Henrique Barboza uint32_t summary; 874fd38804bSDaniel Henrique Barboza uint32_t extended_length; 875fd38804bSDaniel Henrique Barboza void *extended_log; 876ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 87731fe14d1SNathan Fontenot }; 87831fe14d1SNathan Fontenot 8790c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 880ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 881ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 882ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 8838897ea5aSDavid Gibson void spapr_setup_hpt(SpaprMachineState *spapr); 884ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 885068479e1SFabiano Rosas void spapr_check_mmu_mode(bool guest_radix); 886ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 887ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 888df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 889df7625d4SAlexey Kardashevskiy uint32_t nb_table); 890ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 891ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 892c10325d6SDavid Gibson 893ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 8940d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 8950d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 8960d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 897ce2918cbSDavid Gibson SpaprTceTable *tcet); 898c4c81d7dSGreg Kurz void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 899ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 900ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 901ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 9027a36ae7aSBharata B Rao uint32_t count); 903ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 9047a36ae7aSBharata B Rao uint32_t count); 905ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 906afdbd403SBharata B Rao uint32_t count, uint32_t index); 907ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 908afdbd403SBharata B Rao uint32_t count, uint32_t index); 9090b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 910a4e3a7c0SGreg Kurz int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 911ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 912ad334d89SGreg Kurz void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 913eb7f80fdSDaniel Henrique Barboza void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 914ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 915a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 916a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 91781fe70e4SAravinda Prasad void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 91828df36a1SDavid Gibson 91962d38c9bSGreg Kurz /* DRC callbacks. */ 92031834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 921ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 922345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 92331834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 924ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 92562d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 926bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 927ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 928bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 92931834723SDaniel Henrique Barboza 930ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 931ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 93228df36a1SDavid Gibson 933147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 9340d09e41aSPaolo Bonzini 935e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 936db4ef288SBharata B Rao 9374a1c9cf0SBharata B Rao /* 9384a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 9394a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 9404a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 9414a1c9cf0SBharata B Rao */ 9424a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 9434a1c9cf0SBharata B Rao 944ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 945ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 9464a1c9cf0SBharata B Rao 94703d196b7SBharata B Rao /* 94803d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 94903d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 95003d196b7SBharata B Rao */ 95103d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 95203d196b7SBharata B Rao 95303d196b7SBharata B Rao /* 954d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 955d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 95603d196b7SBharata B Rao */ 95703d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 958d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 959d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 9600911a60cSLeonardo Bras #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 96103d196b7SBharata B Rao 9621c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 9631c7ad77eSNicholas Piggin 9640b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 9650b0b8310SDavid Gibson 96614bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 967cfdc5274SGreg Kurz bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 9682e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 9692e886fb3SSam Bobroff 9704e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 9714e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 9724e5fe368SSuraj Jitindar Singh 97333face6bSDavid Gibson /* 97433face6bSDavid Gibson * Handling of optional capabilities 97533face6bSDavid Gibson */ 9764e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 9774e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 9784e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 9798f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 98009114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 9814be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 98264d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 983b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 984c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 9858ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 9869d953ce4SAravinda Prasad extern const VMStateDescription vmstate_spapr_cap_fwnmi; 98782123b75SBharata B Rao extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 98881b205ceSAlexey Kardashevskiy extern const VMStateDescription vmstate_spapr_wdt; 989be85537dSDavid Gibson 990ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 99133face6bSDavid Gibson { 9924e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 99333face6bSDavid Gibson } 99433face6bSDavid Gibson 995ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 996ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 997ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 99840c2281cSMarkus Armbruster void spapr_caps_add_properties(SpaprMachineClass *smc); 999ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 100033face6bSDavid Gibson 100135dce34fSGreg Kurz bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1002123eec65SDavid Gibson Error **errp); 1003db592b5bSCédric Le Goater /* 1004db592b5bSCédric Le Goater * XIVE definitions 1005db592b5bSCédric Le Goater */ 1006db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 1007db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1008db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1009123eec65SDavid Gibson 101000fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 10119c7b7f01SNicholas Piggin void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); 101281fe70e4SAravinda Prasad hwaddr spapr_get_rtas_addr(void); 101373598c75SGreg Kurz bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1014fc8c745dSAlexey Kardashevskiy 101521bde1ecSAlexey Kardashevskiy void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1016fc8c745dSAlexey Kardashevskiy void spapr_vof_quiesce(MachineState *ms); 1017fc8c745dSAlexey Kardashevskiy bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1018fc8c745dSAlexey Kardashevskiy void *val, int vallen); 1019fc8c745dSAlexey Kardashevskiy target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1020fc8c745dSAlexey Kardashevskiy target_ulong opcode, target_ulong *args); 1021fc8c745dSAlexey Kardashevskiy target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1022fc8c745dSAlexey Kardashevskiy CPUState *cs, 1023fc8c745dSAlexey Kardashevskiy target_ulong ovec_addr); 1024fc8c745dSAlexey Kardashevskiy void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1025fc8c745dSAlexey Kardashevskiy 102681b205ceSAlexey Kardashevskiy /* H_WATCHDOG */ 102781b205ceSAlexey Kardashevskiy void spapr_watchdog_init(SpaprMachineState *spapr); 102881b205ceSAlexey Kardashevskiy 10292a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 1030