12a6a4076SMarkus Armbruster #ifndef HW_SPAPR_H 22a6a4076SMarkus Armbruster #define HW_SPAPR_H 30d09e41aSPaolo Bonzini 4ab3dd749SPhilippe Mathieu-Daudé #include "qemu/units.h" 50d09e41aSPaolo Bonzini #include "sysemu/dma.h" 628e02042SDavid Gibson #include "hw/boards.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 9facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 1082cffa2eSCédric Le Goater #include "hw/ppc/spapr_irq.h" 11ce2918cbSDavid Gibson #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 120d8d6a24SThomas Huth #include "hw/ppc/xics.h" /* For ICSState */ 130fb6bd07SMichael Roth #include "hw/ppc/spapr_tpm_proxy.h" 140d09e41aSPaolo Bonzini 15ce2918cbSDavid Gibson struct SpaprVioBus; 16ce2918cbSDavid Gibson struct SpaprPhbState; 17ce2918cbSDavid Gibson struct SpaprNvram; 180d8d6a24SThomas Huth 19ce2918cbSDavid Gibson typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20ce2918cbSDavid Gibson typedef struct SpaprEventSource SpaprEventSource; 21ce2918cbSDavid Gibson typedef struct SpaprPendingHpt SpaprPendingHpt; 220d09e41aSPaolo Bonzini 234be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 241b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 254be21d56SDavid Gibson 26afd10a0fSBharata B Rao #define SPAPR_TIMEBASE_FREQ 512000000ULL 27afd10a0fSBharata B Rao 28147ff807SCédric Le Goater #define TYPE_SPAPR_RTC "spapr-rtc" 29147ff807SCédric Le Goater 30147ff807SCédric Le Goater #define SPAPR_RTC(obj) \ 31ce2918cbSDavid Gibson OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32147ff807SCédric Le Goater 33ce2918cbSDavid Gibson typedef struct SpaprRtcState SpaprRtcState; 34ce2918cbSDavid Gibson struct SpaprRtcState { 35147ff807SCédric Le Goater /*< private >*/ 36147ff807SCédric Le Goater DeviceState parent_obj; 37147ff807SCédric Le Goater int64_t ns_offset; 38147ff807SCédric Le Goater }; 39147ff807SCédric Le Goater 40ce2918cbSDavid Gibson typedef struct SpaprDimmState SpaprDimmState; 41ce2918cbSDavid Gibson typedef struct SpaprMachineClass SpaprMachineClass; 4228e02042SDavid Gibson 4328e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 4428e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 45ce2918cbSDavid Gibson OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 46183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 47ce2918cbSDavid Gibson OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 48183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 49ce2918cbSDavid Gibson OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 50183930c0SDavid Gibson 5130f4b05bSDavid Gibson typedef enum { 5230f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DEFAULT = 0, 5330f4b05bSDavid Gibson SPAPR_RESIZE_HPT_DISABLED, 5430f4b05bSDavid Gibson SPAPR_RESIZE_HPT_ENABLED, 5530f4b05bSDavid Gibson SPAPR_RESIZE_HPT_REQUIRED, 56ce2918cbSDavid Gibson } SpaprResizeHpt; 5730f4b05bSDavid Gibson 58183930c0SDavid Gibson /** 5933face6bSDavid Gibson * Capabilities 6033face6bSDavid Gibson */ 6133face6bSDavid Gibson 62ee76a09fSDavid Gibson /* Hardware Transactional Memory */ 634e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_HTM 0x00 6429386642SDavid Gibson /* Vector Scalar Extensions */ 654e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_VSX 0x01 662d1fb9bcSDavid Gibson /* Decimal Floating Point */ 674e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_DFP 0x02 688f38eaf8SSuraj Jitindar Singh /* Cache Flush on Privilege Change */ 698f38eaf8SSuraj Jitindar Singh #define SPAPR_CAP_CFPC 0x03 7009114fd8SSuraj Jitindar Singh /* Speculation Barrier Bounds Checking */ 7109114fd8SSuraj Jitindar Singh #define SPAPR_CAP_SBBC 0x04 724be8d4e7SSuraj Jitindar Singh /* Indirect Branch Serialisation */ 734be8d4e7SSuraj Jitindar Singh #define SPAPR_CAP_IBS 0x05 742309832aSDavid Gibson /* HPT Maximum Page Size (encoded as a shift) */ 752309832aSDavid Gibson #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 76b9a477b7SSuraj Jitindar Singh /* Nested KVM-HV */ 77b9a477b7SSuraj Jitindar Singh #define SPAPR_CAP_NESTED_KVM_HV 0x07 78c982f5cfSSuraj Jitindar Singh /* Large Decrementer */ 79c982f5cfSSuraj Jitindar Singh #define SPAPR_CAP_LARGE_DECREMENTER 0x08 808ff43ee4SSuraj Jitindar Singh /* Count Cache Flush Assist HW Instruction */ 818ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_CCF_ASSIST 0x09 824e5fe368SSuraj Jitindar Singh /* Num Caps */ 838ff43ee4SSuraj Jitindar Singh #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) 844e5fe368SSuraj Jitindar Singh 854e5fe368SSuraj Jitindar Singh /* 864e5fe368SSuraj Jitindar Singh * Capability Values 874e5fe368SSuraj Jitindar Singh */ 884e5fe368SSuraj Jitindar Singh /* Bool Caps */ 894e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_OFF 0x00 904e5fe368SSuraj Jitindar Singh #define SPAPR_CAP_ON 0x01 91399b2896SSuraj Jitindar Singh 92c76c0d30SSuraj Jitindar Singh /* Custom Caps */ 93399b2896SSuraj Jitindar Singh 94399b2896SSuraj Jitindar Singh /* Generic */ 956898aed7SSuraj Jitindar Singh #define SPAPR_CAP_BROKEN 0x00 966898aed7SSuraj Jitindar Singh #define SPAPR_CAP_WORKAROUND 0x01 976898aed7SSuraj Jitindar Singh #define SPAPR_CAP_FIXED 0x02 98399b2896SSuraj Jitindar Singh /* SPAPR_CAP_IBS (cap-ibs) */ 99c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_IBS 0x02 100c76c0d30SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_CCD 0x03 101399b2896SSuraj Jitindar Singh #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 1022d1fb9bcSDavid Gibson 103ce2918cbSDavid Gibson typedef struct SpaprCapabilities SpaprCapabilities; 104ce2918cbSDavid Gibson struct SpaprCapabilities { 1054e5fe368SSuraj Jitindar Singh uint8_t caps[SPAPR_CAP_NUM]; 10633face6bSDavid Gibson }; 10733face6bSDavid Gibson 10833face6bSDavid Gibson /** 109ce2918cbSDavid Gibson * SpaprMachineClass: 110183930c0SDavid Gibson */ 111ce2918cbSDavid Gibson struct SpaprMachineClass { 112183930c0SDavid Gibson /*< private >*/ 113183930c0SDavid Gibson MachineClass parent_class; 114183930c0SDavid Gibson 115183930c0SDavid Gibson /*< public >*/ 116224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 117962b6c36SMichael Roth bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 118fea35ca4SAlexey Kardashevskiy bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 11957040d45SThomas Huth bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 12046f7afa3SGreg Kurz bool pre_2_10_has_unused_icps; 12182cffa2eSCédric Le Goater bool legacy_irq_allocation; 12254255c1fSDavid Gibson uint32_t nr_xirqs; 1230a794529SDavid Gibson bool broken_host_serial_model; /* present real host info to the guest */ 1243725ef1aSGreg Kurz bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 1256c3829a2SAlexey Kardashevskiy bool linux_pci_probe; 12629cb4187SGreg Kurz bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 12782cffa2eSCédric Le Goater 128ce2918cbSDavid Gibson void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 129daa23699SDavid Gibson uint64_t *buid, hwaddr *pio, 130daa23699SDavid Gibson hwaddr *mmio32, hwaddr *mmio64, 131ec132efaSAlexey Kardashevskiy unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 132ec132efaSAlexey Kardashevskiy hwaddr *nv2atsd, Error **errp); 133ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt_default; 134ce2918cbSDavid Gibson SpaprCapabilities default_caps; 135ce2918cbSDavid Gibson SpaprIrq *irq; 136183930c0SDavid Gibson }; 13728e02042SDavid Gibson 13828e02042SDavid Gibson /** 139ce2918cbSDavid Gibson * SpaprMachineState: 14028e02042SDavid Gibson */ 141ce2918cbSDavid Gibson struct SpaprMachineState { 14228e02042SDavid Gibson /*< private >*/ 14328e02042SDavid Gibson MachineState parent_obj; 14428e02042SDavid Gibson 145ce2918cbSDavid Gibson struct SpaprVioBus *vio_bus; 146ce2918cbSDavid Gibson QLIST_HEAD(, SpaprPhbState) phbs; 147ce2918cbSDavid Gibson struct SpaprNvram *nvram; 148ce2918cbSDavid Gibson SpaprRtcState rtc; 1490d09e41aSPaolo Bonzini 150ce2918cbSDavid Gibson SpaprResizeHpt resize_hpt; 1510d09e41aSPaolo Bonzini void *htab; 1524be21d56SDavid Gibson uint32_t htab_shift; 1539861bb3eSSuraj Jitindar Singh uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 154ce2918cbSDavid Gibson SpaprPendingHpt *pending_hpt; /* in-progress resize */ 1550b0b8310SDavid Gibson 1560d09e41aSPaolo Bonzini hwaddr rma_size; 1570d09e41aSPaolo Bonzini int vrma_adjust; 158fea35ca4SAlexey Kardashevskiy uint32_t fdt_size; 159fea35ca4SAlexey Kardashevskiy uint32_t fdt_initial_size; 160fea35ca4SAlexey Kardashevskiy void *fdt_blob; 161a19f7fb0SDavid Gibson long kernel_size; 162a19f7fb0SDavid Gibson bool kernel_le; 163a19f7fb0SDavid Gibson uint32_t initrd_base; 164a19f7fb0SDavid Gibson long initrd_size; 165880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 16698a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 1670d09e41aSPaolo Bonzini bool has_graphics; 168fa98fbfcSSam Bobroff uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 1690d09e41aSPaolo Bonzini 1700d09e41aSPaolo Bonzini Notifier epow_notifier; 171ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 172ffbb1705SMichael Roth bool use_hotplug_event_source; 173ce2918cbSDavid Gibson SpaprEventSource *event_sources; 1744be21d56SDavid Gibson 1757843c0d6SDavid Gibson /* ibm,client-architecture-support option negotiation */ 1767843c0d6SDavid Gibson bool cas_reboot; 177daa36379SDavid Gibson bool cas_pre_isa3_guest; 178ce2918cbSDavid Gibson SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 179ce2918cbSDavid Gibson SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 1807843c0d6SDavid Gibson uint32_t max_compat_pvr; 1817843c0d6SDavid Gibson 1824be21d56SDavid Gibson /* Migration state */ 1834be21d56SDavid Gibson int htab_save_index; 1844be21d56SDavid Gibson bool htab_first_pass; 185e68cb8b4SAlexey Kardashevskiy int htab_fd; 18646503c2bSMichael Roth 1870cffce56SDavid Gibson /* Pending DIMM unplug cache. It is populated when a LMB 1880cffce56SDavid Gibson * unplug starts. It can be regenerated if a migration 1890cffce56SDavid Gibson * occurs during the unplug process. */ 190ce2918cbSDavid Gibson QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 1910cffce56SDavid Gibson 19228e02042SDavid Gibson /*< public >*/ 19328e02042SDavid Gibson char *kvm_type; 19427461d69SPrasad J Pandit char *host_model; 19527461d69SPrasad J Pandit char *host_serial; 196852ad27eSCédric Le Goater 19782cffa2eSCédric Le Goater int32_t irq_map_nr; 19882cffa2eSCédric Le Goater unsigned long *irq_map; 199ce2918cbSDavid Gibson SpaprIrq *irq; 200872ff3deSCédric Le Goater qemu_irq *qirqs; 20181106dddSDavid Gibson SpaprInterruptController *active_intc; 20281106dddSDavid Gibson ICSState *ics; 20381106dddSDavid Gibson SpaprXive *xive; 20433face6bSDavid Gibson 2054e5fe368SSuraj Jitindar Singh bool cmd_line_caps[SPAPR_CAP_NUM]; 206ce2918cbSDavid Gibson SpaprCapabilities def, eff, mig; 207ec132efaSAlexey Kardashevskiy 208ec132efaSAlexey Kardashevskiy unsigned gpu_numa_id; 2090fb6bd07SMichael Roth SpaprTpmProxy *tpm_proxy; 21028e02042SDavid Gibson }; 2110d09e41aSPaolo Bonzini 2120d09e41aSPaolo Bonzini #define H_SUCCESS 0 2130d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 2140d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 2150d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 2160d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 2170d09e41aSPaolo Bonzini #define H_PARTIAL 5 2180d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 2190d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 2200d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 2210d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 2220d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 2230d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 2240d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 2250d09e41aSPaolo Bonzini is a good time to retry */ 2260d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 2270d09e41aSPaolo Bonzini is a good time to retry */ 2280d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 2290d09e41aSPaolo Bonzini is a good time to retry */ 2300d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 2310d09e41aSPaolo Bonzini is a good time to retry */ 2320d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 2330d09e41aSPaolo Bonzini is a good time to retry */ 2340d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 2350d09e41aSPaolo Bonzini is a good time to retry */ 2360d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 2370d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 2380d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 2390d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 2400d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 2410d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 2420d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 2430d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 2440d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 2450d09e41aSPaolo Bonzini #define H_NO_MEM -9 2460d09e41aSPaolo Bonzini #define H_AUTHORITY -10 2470d09e41aSPaolo Bonzini #define H_PERMISSION -11 2480d09e41aSPaolo Bonzini #define H_DROPPED -12 2490d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 2500d09e41aSPaolo Bonzini #define H_DEST_PARM -14 2510d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 2520d09e41aSPaolo Bonzini #define H_RESOURCE -16 2530d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 2540d09e41aSPaolo Bonzini #define H_RH_PARM -18 2550d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 2560d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 2570d09e41aSPaolo Bonzini #define H_EQ_PARM -21 2580d09e41aSPaolo Bonzini #define H_RT_PARM -22 2590d09e41aSPaolo Bonzini #define H_ST_PARM -23 2600d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 2610d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 2620d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 2630d09e41aSPaolo Bonzini #define H_MEM_PARM -28 2640d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 2650d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 2660d09e41aSPaolo Bonzini #define H_PORT_PARM -31 2670d09e41aSPaolo Bonzini #define H_MCG_PARM -32 2680d09e41aSPaolo Bonzini #define H_VL_PARM -33 2690d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 2700d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 2710d09e41aSPaolo Bonzini 2720d09e41aSPaolo Bonzini #define H_MASK_PARM -37 2730d09e41aSPaolo Bonzini #define H_MCG_FULL -38 2740d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 2750d09e41aSPaolo Bonzini #define H_P_COUNTER -40 2760d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 2770d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 2780d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 2790d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 2800d09e41aSPaolo Bonzini #define H_R_STATE -45 2810d09e41aSPaolo Bonzini #define H_RESCINDEND -46 28242561bf2SAnton Blanchard #define H_P2 -55 28342561bf2SAnton Blanchard #define H_P3 -56 28442561bf2SAnton Blanchard #define H_P4 -57 28542561bf2SAnton Blanchard #define H_P5 -58 28642561bf2SAnton Blanchard #define H_P6 -59 28742561bf2SAnton Blanchard #define H_P7 -60 28842561bf2SAnton Blanchard #define H_P8 -61 28942561bf2SAnton Blanchard #define H_P9 -62 29042561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 2910d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 2920d09e41aSPaolo Bonzini 2930d09e41aSPaolo Bonzini 2940d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 2950d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 2960d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 2970d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 2980d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 2990d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 3000d09e41aSPaolo Bonzini * way to check for the long_busy return codes 3010d09e41aSPaolo Bonzini */ 3020d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 3030d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 3040d09e41aSPaolo Bonzini 3050d09e41aSPaolo Bonzini /* Flags */ 3060d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 3070d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 3080d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 3090d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 3100d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 3110d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 3120d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 3130d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 3140d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 3150d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 3160d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 3170d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 3180d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 3190d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 3200d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 3210d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 3220d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 3230d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 3240d09e41aSPaolo Bonzini 325a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 326a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 327a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 328a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 329a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 330a46622fdSAlexey Kardashevskiy 331a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 33242561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 33342561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 33442561bf2SAnton Blanchard 3350d09e41aSPaolo Bonzini /* VASI States */ 3360d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 3370d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 3380d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 3390d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 3400d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 3410d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 3420d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 3430d09e41aSPaolo Bonzini 3440d09e41aSPaolo Bonzini /* DABRX flags */ 3450d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 3460d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 3470d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 3480d09e41aSPaolo Bonzini 3498acc2ae5SSuraj Jitindar Singh /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 3508acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 3518acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 3528acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 3538acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 3548acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 3558acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 3568acc2ae5SSuraj Jitindar Singh #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 357c76c0d30SSuraj Jitindar Singh #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 358399b2896SSuraj Jitindar Singh #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 3598acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 3608acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 3618acc2ae5SSuraj Jitindar Singh #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 362399b2896SSuraj Jitindar Singh #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 3638acc2ae5SSuraj Jitindar Singh 3640d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 3650d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 3660d09e41aSPaolo Bonzini 3670d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 3680d09e41aSPaolo Bonzini #define H_REMOVE 0x04 3690d09e41aSPaolo Bonzini #define H_ENTER 0x08 3700d09e41aSPaolo Bonzini #define H_READ 0x0c 3710d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 3720d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 3730d09e41aSPaolo Bonzini #define H_PROTECT 0x18 3740d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 3750d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 3760d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 3770d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 3780d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 3790d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 3800d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 3810d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 3820d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 3830d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 3840d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 3850d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 3860d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 3870d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 3880d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 3890d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 3900d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 3910d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 3920d09e41aSPaolo Bonzini #define H_EOI 0x64 3930d09e41aSPaolo Bonzini #define H_CPPR 0x68 3940d09e41aSPaolo Bonzini #define H_IPI 0x6c 3950d09e41aSPaolo Bonzini #define H_IPOLL 0x70 3960d09e41aSPaolo Bonzini #define H_XIRR 0x74 3970d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 3980d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 3990d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 4000d09e41aSPaolo Bonzini #define H_CEDE 0xE0 4010d09e41aSPaolo Bonzini #define H_CONFER 0xE4 4020d09e41aSPaolo Bonzini #define H_PROD 0xE8 4030d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 4040d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 4050d09e41aSPaolo Bonzini #define H_PURR 0xF4 4060d09e41aSPaolo Bonzini #define H_PIC 0xF8 4070d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 4080d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 4090d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 4100d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 4110d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 4120d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 4130d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 4140d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 4150d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 4160d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 4170d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 4180d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 4190d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 4200d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 4210d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 4220d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 4230d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 4240d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 4250d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 4260d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 4270d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 4280d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 4290d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 4300d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 4310d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 4320d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 4330d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 4340d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 4350d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 4360d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 4370d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 4380d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 4390d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 4400d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 4410d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 4420d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 4430d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 4440d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 4450d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 4460d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 4470d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 4480d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 4490d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 4500d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 451c59704b2SSuraj Jitindar Singh #define H_GET_CPU_CHARACTERISTICS 0x1C8 4520d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 4530d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 4540d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 4550d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 4560d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 4570d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 4580d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 4590d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 4600d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 4610d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 4620d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 4630d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 4640d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 4650d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 4660d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 4670d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 4680d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 4690d09e41aSPaolo Bonzini #define H_JOIN 0x298 4700d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 4710d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 4720d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 4730d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 4740d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 475c24ba3d0SLaurent Vivier #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 4765d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 4774d9392beSThomas Huth #define H_RANDOM 0x300 47842561bf2SAnton Blanchard #define H_SET_MODE 0x31C 47930f4b05bSDavid Gibson #define H_RESIZE_HPT_PREPARE 0x36C 48030f4b05bSDavid Gibson #define H_RESIZE_HPT_COMMIT 0x370 481d77a98b0SSuraj Jitindar Singh #define H_CLEAN_SLB 0x374 482d77a98b0SSuraj Jitindar Singh #define H_INVALIDATE_PID 0x378 483d77a98b0SSuraj Jitindar Singh #define H_REGISTER_PROC_TBL 0x37C 4841c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET 0x380 48523bcd5ebSCédric Le Goater 48623bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_INFO 0x3A8 48723bcd5ebSCédric Le Goater #define H_INT_SET_SOURCE_CONFIG 0x3AC 48823bcd5ebSCédric Le Goater #define H_INT_GET_SOURCE_CONFIG 0x3B0 48923bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_INFO 0x3B4 49023bcd5ebSCédric Le Goater #define H_INT_SET_QUEUE_CONFIG 0x3B8 49123bcd5ebSCédric Le Goater #define H_INT_GET_QUEUE_CONFIG 0x3BC 49223bcd5ebSCédric Le Goater #define H_INT_SET_OS_REPORTING_LINE 0x3C0 49323bcd5ebSCédric Le Goater #define H_INT_GET_OS_REPORTING_LINE 0x3C4 49423bcd5ebSCédric Le Goater #define H_INT_ESB 0x3C8 49523bcd5ebSCédric Le Goater #define H_INT_SYNC 0x3CC 49623bcd5ebSCédric Le Goater #define H_INT_RESET 0x3D0 49723bcd5ebSCédric Le Goater 49823bcd5ebSCédric Le Goater #define MAX_HCALL_OPCODE H_INT_RESET 4990d09e41aSPaolo Bonzini 5000d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 5010d09e41aSPaolo Bonzini * as well. 5020d09e41aSPaolo Bonzini * 5030d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 504498cd995SGreg Kurz * We put those into the 0xf000-0xfffc range which is reserved by PAPR 505498cd995SGreg Kurz * for "platform-specific" hcalls. 5060d09e41aSPaolo Bonzini */ 5070d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 5080d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 5090d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 5102a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 5112a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 512fea35ca4SAlexey Kardashevskiy #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 513fea35ca4SAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 5140d09e41aSPaolo Bonzini 5150fb6bd07SMichael Roth /* 5160fb6bd07SMichael Roth * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 5170fb6bd07SMichael Roth * Secure VM mode via an Ultravisor / Protected Execution Facility 5180fb6bd07SMichael Roth */ 5190fb6bd07SMichael Roth #define SVM_HCALL_BASE 0xEF00 5200fb6bd07SMichael Roth #define SVM_H_TPM_COMM 0xEF10 5210fb6bd07SMichael Roth #define SVM_HCALL_MAX SVM_H_TPM_COMM 5220fb6bd07SMichael Roth 5230fb6bd07SMichael Roth 524ce2918cbSDavid Gibson typedef struct SpaprDeviceTreeUpdateHeader { 5252a6593cbSAlexey Kardashevskiy uint32_t version_id; 526ce2918cbSDavid Gibson } SpaprDeviceTreeUpdateHeader; 5272a6593cbSAlexey Kardashevskiy 5280d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 529aaf87c66SThomas Huth do { \ 530aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 531aaf87c66SThomas Huth } while (0) 5320d09e41aSPaolo Bonzini 533ce2918cbSDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 5340d09e41aSPaolo Bonzini target_ulong opcode, 5350d09e41aSPaolo Bonzini target_ulong *args); 5360d09e41aSPaolo Bonzini 5370d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 5380d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 5390d09e41aSPaolo Bonzini target_ulong *args); 5400d09e41aSPaolo Bonzini 54103ef074cSNicholas Piggin /* Virtual Processor Area structure constants */ 54203ef074cSNicholas Piggin #define VPA_MIN_SIZE 640 54303ef074cSNicholas Piggin #define VPA_SIZE_OFFSET 0x4 54403ef074cSNicholas Piggin #define VPA_SHARED_PROC_OFFSET 0x9 54503ef074cSNicholas Piggin #define VPA_SHARED_PROC_VAL 0x2 54603ef074cSNicholas Piggin #define VPA_DISPATCH_COUNTER 0x100 54703ef074cSNicholas Piggin 548ee954280SGavin Shan /* ibm,set-eeh-option */ 549ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 550ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 551ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 552ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 553ee954280SGavin Shan 554ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 555ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 556ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 557ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 558ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 559ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 560ee954280SGavin Shan 561ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 562ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 563ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 564ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 565ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 566ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 567ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 568ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 569ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 570ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 571ee954280SGavin Shan 572ee954280SGavin Shan /* ibm,set-slot-reset */ 573ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 574ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 575ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 576ee954280SGavin Shan 577ee954280SGavin Shan /* ibm,slot-error-detail */ 578ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 579ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 580ee954280SGavin Shan 581a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 582a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 583a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 584a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 585a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 586a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 5873ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 5889d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 5893ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 590c920f7b4SDavid Gibson #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 591a64d325dSAlexey Kardashevskiy 592ae4de14cSAlexey Kardashevskiy /* DDW pagesize mask values from ibm,query-pe-dma-window */ 593ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_4K 0x01 594ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64K 0x02 595ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16M 0x04 596ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_32M 0x08 597ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_64M 0x10 598ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_128M 0x20 599ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_256M 0x40 600ae4de14cSAlexey Kardashevskiy #define RTAS_DDW_PGSIZE_16G 0x80 601ae4de14cSAlexey Kardashevskiy 6023a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 6033a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 6043a3b8502SAlexey Kardashevskiy 6053a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 6063a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 6073a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 6083a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 6093a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 6103a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 6113a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 6123a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 6133a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 6143a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 6153a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 6163a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 6173a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 6183a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 6193a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 6203a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 6213a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 6223a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 6233a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 6243a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 6253a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 6263a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 6273a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 6283a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 6293a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 6303a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 6313a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 6323a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 6333a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 6343a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 6353a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 6363a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 637ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 638ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 639ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 640ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 641ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 642ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 643ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 644ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 645ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 646ae4de14cSAlexey Kardashevskiy #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 64793eac7b8SNicholas Piggin #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 6483a3b8502SAlexey Kardashevskiy 64993eac7b8SNicholas Piggin #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2B) 6503a3b8502SAlexey Kardashevskiy 6513052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 6523b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 6533052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 654b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 6553052d951SSam bobroff 6568c8639dfSMike Day /* RTAS indicator/sensor types 6578c8639dfSMike Day * 6588c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 6598c8639dfSMike Day * 6608c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 6618c8639dfSMike Day */ 6628c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 6638c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 6648c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 6658c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 6668c8639dfSMike Day 6673052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 6683052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 6693052d951SSam bobroff */ 6703052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 6713052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 6723052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 6733052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 6743052d951SSam bobroff 6754fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 6764fe822e0SAlexey Kardashevskiy { 6774fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 6784fe822e0SAlexey Kardashevskiy } 6794fe822e0SAlexey Kardashevskiy 6800d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 6810d09e41aSPaolo Bonzini { 682fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 6830d09e41aSPaolo Bonzini } 6840d09e41aSPaolo Bonzini 685a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 686a14aa92bSGavin Shan { 687a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 688a14aa92bSGavin Shan } 689a14aa92bSGavin Shan 6900d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 6910d09e41aSPaolo Bonzini { 692ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 6930d09e41aSPaolo Bonzini } 6940d09e41aSPaolo Bonzini 695ce2918cbSDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 696210b580bSAnthony Liguori uint32_t token, 6970d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 6980d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 6993a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 700ce2918cbSDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 7010d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 7020d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 7033f5dabceSDavid Gibson void spapr_dt_rtas_tokens(void *fdt, int rtas); 704ce2918cbSDavid Gibson void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 7050d09e41aSPaolo Bonzini 7060d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 7070d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 7080d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 7090d09e41aSPaolo Bonzini 7100d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 7114290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 712c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 713c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 714d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 715c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 7160d09e41aSPaolo Bonzini 7170d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 7180d09e41aSPaolo Bonzini 71979853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 72079853e18STyrel Datwyler 721bb2d8ab6SGreg Kurz /* This helper should be used to encode interrupt specifiers when the related 722bb2d8ab6SGreg Kurz * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 723bb2d8ab6SGreg Kurz * VIO devices, RTAS event sources and PHBs). 724bb2d8ab6SGreg Kurz */ 7255c7adcf4SGreg Kurz static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 726bb2d8ab6SGreg Kurz { 727bb2d8ab6SGreg Kurz intspec[0] = cpu_to_be32(irq); 728bb2d8ab6SGreg Kurz intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 729bb2d8ab6SGreg Kurz } 730bb2d8ab6SGreg Kurz 731ce2918cbSDavid Gibson typedef struct SpaprTceTable SpaprTceTable; 7320d09e41aSPaolo Bonzini 733a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 734a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 735ce2918cbSDavid Gibson OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 736a83000f5SAnthony Liguori 7371221a474SAlexey Kardashevskiy #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 7381221a474SAlexey Kardashevskiy #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 7391221a474SAlexey Kardashevskiy OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 7401221a474SAlexey Kardashevskiy 741ce2918cbSDavid Gibson struct SpaprTceTable { 742a83000f5SAnthony Liguori DeviceState parent; 743a83000f5SAnthony Liguori uint32_t liobn; 744a83000f5SAnthony Liguori uint32_t nb_table; 7451b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 746650f33adSAlexey Kardashevskiy uint32_t page_shift; 747a83000f5SAnthony Liguori uint64_t *table; 748a26fdf39SAlexey Kardashevskiy uint32_t mig_nb_table; 749a26fdf39SAlexey Kardashevskiy uint64_t *mig_table; 750a83000f5SAnthony Liguori bool bypass; 7516a81dd17SDavid Gibson bool need_vfio; 7525f366667SAlexey Kardashevskiy bool skipping_replay; 753a83000f5SAnthony Liguori int fd; 7543df9d748SAlexey Kardashevskiy MemoryRegion root; 7553df9d748SAlexey Kardashevskiy IOMMUMemoryRegion iommu; 756ce2918cbSDavid Gibson struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 757ce2918cbSDavid Gibson QLIST_ENTRY(SpaprTceTable) list; 758a83000f5SAnthony Liguori }; 759a83000f5SAnthony Liguori 760ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 76131fe14d1SNathan Fontenot 762ce2918cbSDavid Gibson struct SpaprEventLogEntry { 763fd38804bSDaniel Henrique Barboza uint32_t summary; 764fd38804bSDaniel Henrique Barboza uint32_t extended_length; 765fd38804bSDaniel Henrique Barboza void *extended_log; 766ce2918cbSDavid Gibson QTAILQ_ENTRY(SpaprEventLogEntry) next; 76731fe14d1SNathan Fontenot }; 76831fe14d1SNathan Fontenot 769*0c21e073SDavid Gibson void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 770ce2918cbSDavid Gibson void spapr_events_init(SpaprMachineState *sm); 771ce2918cbSDavid Gibson void spapr_dt_events(SpaprMachineState *sm, void *fdt); 772ce2918cbSDavid Gibson void close_htab_fd(SpaprMachineState *spapr); 773ce2918cbSDavid Gibson void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); 774ce2918cbSDavid Gibson void spapr_free_hpt(SpaprMachineState *spapr); 775ce2918cbSDavid Gibson SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 776ce2918cbSDavid Gibson void spapr_tce_table_enable(SpaprTceTable *tcet, 777df7625d4SAlexey Kardashevskiy uint32_t page_shift, uint64_t bus_offset, 778df7625d4SAlexey Kardashevskiy uint32_t nb_table); 779ce2918cbSDavid Gibson void spapr_tce_table_disable(SpaprTceTable *tcet); 780ce2918cbSDavid Gibson void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 781c10325d6SDavid Gibson 782ce2918cbSDavid Gibson MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 7830d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 7840d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 7850d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 786ce2918cbSDavid Gibson SpaprTceTable *tcet); 787eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 788ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 789ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 790ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 7917a36ae7aSBharata B Rao uint32_t count); 792ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 7937a36ae7aSBharata B Rao uint32_t count); 794ce2918cbSDavid Gibson void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 795afdbd403SBharata B Rao uint32_t count, uint32_t index); 796ce2918cbSDavid Gibson void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 797afdbd403SBharata B Rao uint32_t count, uint32_t index); 7980b0b8310SDavid Gibson int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 799ce2918cbSDavid Gibson void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 8002772cf6bSDavid Gibson Error **errp); 801ce2918cbSDavid Gibson void spapr_clear_pending_events(SpaprMachineState *spapr); 802ce2918cbSDavid Gibson int spapr_max_server_number(SpaprMachineState *spapr); 803a2dd4e83SBenjamin Herrenschmidt void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 804a2dd4e83SBenjamin Herrenschmidt uint64_t pte0, uint64_t pte1); 80528df36a1SDavid Gibson 80662d38c9bSGreg Kurz /* DRC callbacks. */ 80731834723SDaniel Henrique Barboza void spapr_core_release(DeviceState *dev); 808ce2918cbSDavid Gibson int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 809345b12b9SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 81031834723SDaniel Henrique Barboza void spapr_lmb_release(DeviceState *dev); 811ce2918cbSDavid Gibson int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 81262d38c9bSGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 813bb2bdd81SGreg Kurz void spapr_phb_release(DeviceState *dev); 814ce2918cbSDavid Gibson int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 815bb2bdd81SGreg Kurz void *fdt, int *fdt_start_offset, Error **errp); 81631834723SDaniel Henrique Barboza 817ce2918cbSDavid Gibson void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 818ce2918cbSDavid Gibson int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 81928df36a1SDavid Gibson 820147ff807SCédric Le Goater #define TYPE_SPAPR_RNG "spapr-rng" 8210d09e41aSPaolo Bonzini 822e075623aSDavid Gibson #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 823db4ef288SBharata B Rao 8244a1c9cf0SBharata B Rao /* 8254a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 8264a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 8274a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 8284a1c9cf0SBharata B Rao */ 8294a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 8304a1c9cf0SBharata B Rao 831ab3dd749SPhilippe Mathieu-Daudé /* 1GB alignment for hotplug memory region */ 832ab3dd749SPhilippe Mathieu-Daudé #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 8334a1c9cf0SBharata B Rao 83403d196b7SBharata B Rao /* 83503d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 83603d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 83703d196b7SBharata B Rao */ 83803d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 83903d196b7SBharata B Rao 84003d196b7SBharata B Rao /* 841d0e5a8f2SBharata B Rao * Defines for flag value in ibm,dynamic-memory property under 842d0e5a8f2SBharata B Rao * ibm,dynamic-reconfiguration-memory node. 84303d196b7SBharata B Rao */ 84403d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 845d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 846d0e5a8f2SBharata B Rao #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 84703d196b7SBharata B Rao 8481c7ad77eSNicholas Piggin void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 8491c7ad77eSNicholas Piggin 8500b0b8310SDavid Gibson #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 8510b0b8310SDavid Gibson 85214bb4486SGreg Kurz int spapr_get_vcpu_id(PowerPCCPU *cpu); 853648edb64SGreg Kurz void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 8542e886fb3SSam Bobroff PowerPCCPU *spapr_find_cpu(int vcpu_id); 8552e886fb3SSam Bobroff 8564e5fe368SSuraj Jitindar Singh int spapr_caps_pre_load(void *opaque); 8574e5fe368SSuraj Jitindar Singh int spapr_caps_pre_save(void *opaque); 8584e5fe368SSuraj Jitindar Singh 85933face6bSDavid Gibson /* 86033face6bSDavid Gibson * Handling of optional capabilities 86133face6bSDavid Gibson */ 8624e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_htm; 8634e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_vsx; 8644e5fe368SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_dfp; 8658f38eaf8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_cfpc; 86609114fd8SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_sbbc; 8674be8d4e7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ibs; 86864d4a534SDavid Gibson extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 869b9a477b7SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 870c982f5cfSSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_large_decr; 8718ff43ee4SSuraj Jitindar Singh extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 872be85537dSDavid Gibson 873ce2918cbSDavid Gibson static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 87433face6bSDavid Gibson { 8754e5fe368SSuraj Jitindar Singh return spapr->eff.caps[cap]; 87633face6bSDavid Gibson } 87733face6bSDavid Gibson 878ce2918cbSDavid Gibson void spapr_caps_init(SpaprMachineState *spapr); 879ce2918cbSDavid Gibson void spapr_caps_apply(SpaprMachineState *spapr); 880ce2918cbSDavid Gibson void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 881ce2918cbSDavid Gibson void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 882ce2918cbSDavid Gibson int spapr_caps_post_migration(SpaprMachineState *spapr); 88333face6bSDavid Gibson 884ce2918cbSDavid Gibson void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 885123eec65SDavid Gibson Error **errp); 886db592b5bSCédric Le Goater /* 887db592b5bSCédric Le Goater * XIVE definitions 888db592b5bSCédric Le Goater */ 889db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_LEGACY 0x0 890db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_EXPLOIT 0x40 891db592b5bSCédric Le Goater #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 892123eec65SDavid Gibson 89300fd075eSBenjamin Herrenschmidt void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 8942a6a4076SMarkus Armbruster #endif /* HW_SPAPR_H */ 895