10d09e41aSPaolo Bonzini #if !defined(__HW_SPAPR_H__) 20d09e41aSPaolo Bonzini #define __HW_SPAPR_H__ 30d09e41aSPaolo Bonzini 40d09e41aSPaolo Bonzini #include "sysemu/dma.h" 528e02042SDavid Gibson #include "hw/boards.h" 60d09e41aSPaolo Bonzini #include "hw/ppc/xics.h" 731fe14d1SNathan Fontenot #include "hw/ppc/spapr_drc.h" 84a1c9cf0SBharata B Rao #include "hw/mem/pc-dimm.h" 90d09e41aSPaolo Bonzini 100d09e41aSPaolo Bonzini struct VIOsPAPRBus; 110d09e41aSPaolo Bonzini struct sPAPRPHBState; 120d09e41aSPaolo Bonzini struct sPAPRNVRAM; 1346503c2bSMichael Roth typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 1431fe14d1SNathan Fontenot typedef struct sPAPREventLogEntry sPAPREventLogEntry; 150d09e41aSPaolo Bonzini 164be21d56SDavid Gibson #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 171b718907SDavid Gibson #define SPAPR_ENTRY_POINT 0x100 184be21d56SDavid Gibson 19183930c0SDavid Gibson typedef struct sPAPRMachineClass sPAPRMachineClass; 2028e02042SDavid Gibson typedef struct sPAPRMachineState sPAPRMachineState; 2128e02042SDavid Gibson 2228e02042SDavid Gibson #define TYPE_SPAPR_MACHINE "spapr-machine" 2328e02042SDavid Gibson #define SPAPR_MACHINE(obj) \ 2428e02042SDavid Gibson OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 25183930c0SDavid Gibson #define SPAPR_MACHINE_GET_CLASS(obj) \ 26183930c0SDavid Gibson OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 27183930c0SDavid Gibson #define SPAPR_MACHINE_CLASS(klass) \ 28183930c0SDavid Gibson OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 29183930c0SDavid Gibson 30183930c0SDavid Gibson /** 31183930c0SDavid Gibson * sPAPRMachineClass: 32183930c0SDavid Gibson */ 33183930c0SDavid Gibson struct sPAPRMachineClass { 34183930c0SDavid Gibson /*< private >*/ 35183930c0SDavid Gibson MachineClass parent_class; 36183930c0SDavid Gibson 37183930c0SDavid Gibson /*< public >*/ 38224245bfSDavid Gibson bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 39183930c0SDavid Gibson }; 4028e02042SDavid Gibson 4128e02042SDavid Gibson /** 4228e02042SDavid Gibson * sPAPRMachineState: 4328e02042SDavid Gibson */ 4428e02042SDavid Gibson struct sPAPRMachineState { 4528e02042SDavid Gibson /*< private >*/ 4628e02042SDavid Gibson MachineState parent_obj; 4728e02042SDavid Gibson 480d09e41aSPaolo Bonzini struct VIOsPAPRBus *vio_bus; 490d09e41aSPaolo Bonzini QLIST_HEAD(, sPAPRPHBState) phbs; 500d09e41aSPaolo Bonzini struct sPAPRNVRAM *nvram; 51c04d6cfaSAnthony Liguori XICSState *icp; 5228df36a1SDavid Gibson DeviceState *rtc; 530d09e41aSPaolo Bonzini 540d09e41aSPaolo Bonzini void *htab; 554be21d56SDavid Gibson uint32_t htab_shift; 560d09e41aSPaolo Bonzini hwaddr rma_size; 570d09e41aSPaolo Bonzini int vrma_adjust; 580d09e41aSPaolo Bonzini hwaddr fdt_addr, rtas_addr; 59b7d1f77aSBenjamin Herrenschmidt ssize_t rtas_size; 60b7d1f77aSBenjamin Herrenschmidt void *rtas_blob; 610d09e41aSPaolo Bonzini void *fdt_skel; 62880ae7deSDavid Gibson uint64_t rtc_offset; /* Now used only during incoming migration */ 6398a8b524SAlexey Kardashevskiy struct PPCTimebase tb; 640d09e41aSPaolo Bonzini bool has_graphics; 650d09e41aSPaolo Bonzini 6631fe14d1SNathan Fontenot uint32_t check_exception_irq; 670d09e41aSPaolo Bonzini Notifier epow_notifier; 6831fe14d1SNathan Fontenot QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 694be21d56SDavid Gibson 704be21d56SDavid Gibson /* Migration state */ 714be21d56SDavid Gibson int htab_save_index; 724be21d56SDavid Gibson bool htab_first_pass; 73e68cb8b4SAlexey Kardashevskiy int htab_fd; 7401a57972SSamuel Mendoza-Jonas bool htab_fd_stale; 7546503c2bSMichael Roth 7646503c2bSMichael Roth /* RTAS state */ 7746503c2bSMichael Roth QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 7828e02042SDavid Gibson 7928e02042SDavid Gibson /*< public >*/ 8028e02042SDavid Gibson char *kvm_type; 814a1c9cf0SBharata B Rao MemoryHotplugState hotplug_memory; 8228e02042SDavid Gibson }; 830d09e41aSPaolo Bonzini 840d09e41aSPaolo Bonzini #define H_SUCCESS 0 850d09e41aSPaolo Bonzini #define H_BUSY 1 /* Hardware busy -- retry later */ 860d09e41aSPaolo Bonzini #define H_CLOSED 2 /* Resource closed */ 870d09e41aSPaolo Bonzini #define H_NOT_AVAILABLE 3 880d09e41aSPaolo Bonzini #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 890d09e41aSPaolo Bonzini #define H_PARTIAL 5 900d09e41aSPaolo Bonzini #define H_IN_PROGRESS 14 /* Kind of like busy */ 910d09e41aSPaolo Bonzini #define H_PAGE_REGISTERED 15 920d09e41aSPaolo Bonzini #define H_PARTIAL_STORE 16 930d09e41aSPaolo Bonzini #define H_PENDING 17 /* returned from H_POLL_PENDING */ 940d09e41aSPaolo Bonzini #define H_CONTINUE 18 /* Returned from H_Join on success */ 950d09e41aSPaolo Bonzini #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 960d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 970d09e41aSPaolo Bonzini is a good time to retry */ 980d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 990d09e41aSPaolo Bonzini is a good time to retry */ 1000d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 1010d09e41aSPaolo Bonzini is a good time to retry */ 1020d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 1030d09e41aSPaolo Bonzini is a good time to retry */ 1040d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 1050d09e41aSPaolo Bonzini is a good time to retry */ 1060d09e41aSPaolo Bonzini #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 1070d09e41aSPaolo Bonzini is a good time to retry */ 1080d09e41aSPaolo Bonzini #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 1090d09e41aSPaolo Bonzini #define H_HARDWARE -1 /* Hardware error */ 1100d09e41aSPaolo Bonzini #define H_FUNCTION -2 /* Function not supported */ 1110d09e41aSPaolo Bonzini #define H_PRIVILEGE -3 /* Caller not privileged */ 1120d09e41aSPaolo Bonzini #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 1130d09e41aSPaolo Bonzini #define H_BAD_MODE -5 /* Illegal msr value */ 1140d09e41aSPaolo Bonzini #define H_PTEG_FULL -6 /* PTEG is full */ 1150d09e41aSPaolo Bonzini #define H_NOT_FOUND -7 /* PTE was not found" */ 1160d09e41aSPaolo Bonzini #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 1170d09e41aSPaolo Bonzini #define H_NO_MEM -9 1180d09e41aSPaolo Bonzini #define H_AUTHORITY -10 1190d09e41aSPaolo Bonzini #define H_PERMISSION -11 1200d09e41aSPaolo Bonzini #define H_DROPPED -12 1210d09e41aSPaolo Bonzini #define H_SOURCE_PARM -13 1220d09e41aSPaolo Bonzini #define H_DEST_PARM -14 1230d09e41aSPaolo Bonzini #define H_REMOTE_PARM -15 1240d09e41aSPaolo Bonzini #define H_RESOURCE -16 1250d09e41aSPaolo Bonzini #define H_ADAPTER_PARM -17 1260d09e41aSPaolo Bonzini #define H_RH_PARM -18 1270d09e41aSPaolo Bonzini #define H_RCQ_PARM -19 1280d09e41aSPaolo Bonzini #define H_SCQ_PARM -20 1290d09e41aSPaolo Bonzini #define H_EQ_PARM -21 1300d09e41aSPaolo Bonzini #define H_RT_PARM -22 1310d09e41aSPaolo Bonzini #define H_ST_PARM -23 1320d09e41aSPaolo Bonzini #define H_SIGT_PARM -24 1330d09e41aSPaolo Bonzini #define H_TOKEN_PARM -25 1340d09e41aSPaolo Bonzini #define H_MLENGTH_PARM -27 1350d09e41aSPaolo Bonzini #define H_MEM_PARM -28 1360d09e41aSPaolo Bonzini #define H_MEM_ACCESS_PARM -29 1370d09e41aSPaolo Bonzini #define H_ATTR_PARM -30 1380d09e41aSPaolo Bonzini #define H_PORT_PARM -31 1390d09e41aSPaolo Bonzini #define H_MCG_PARM -32 1400d09e41aSPaolo Bonzini #define H_VL_PARM -33 1410d09e41aSPaolo Bonzini #define H_TSIZE_PARM -34 1420d09e41aSPaolo Bonzini #define H_TRACE_PARM -35 1430d09e41aSPaolo Bonzini 1440d09e41aSPaolo Bonzini #define H_MASK_PARM -37 1450d09e41aSPaolo Bonzini #define H_MCG_FULL -38 1460d09e41aSPaolo Bonzini #define H_ALIAS_EXIST -39 1470d09e41aSPaolo Bonzini #define H_P_COUNTER -40 1480d09e41aSPaolo Bonzini #define H_TABLE_FULL -41 1490d09e41aSPaolo Bonzini #define H_ALT_TABLE -42 1500d09e41aSPaolo Bonzini #define H_MR_CONDITION -43 1510d09e41aSPaolo Bonzini #define H_NOT_ENOUGH_RESOURCES -44 1520d09e41aSPaolo Bonzini #define H_R_STATE -45 1530d09e41aSPaolo Bonzini #define H_RESCINDEND -46 15442561bf2SAnton Blanchard #define H_P2 -55 15542561bf2SAnton Blanchard #define H_P3 -56 15642561bf2SAnton Blanchard #define H_P4 -57 15742561bf2SAnton Blanchard #define H_P5 -58 15842561bf2SAnton Blanchard #define H_P6 -59 15942561bf2SAnton Blanchard #define H_P7 -60 16042561bf2SAnton Blanchard #define H_P8 -61 16142561bf2SAnton Blanchard #define H_P9 -62 16242561bf2SAnton Blanchard #define H_UNSUPPORTED_FLAG -256 1630d09e41aSPaolo Bonzini #define H_MULTI_THREADS_ACTIVE -9005 1640d09e41aSPaolo Bonzini 1650d09e41aSPaolo Bonzini 1660d09e41aSPaolo Bonzini /* Long Busy is a condition that can be returned by the firmware 1670d09e41aSPaolo Bonzini * when a call cannot be completed now, but the identical call 1680d09e41aSPaolo Bonzini * should be retried later. This prevents calls blocking in the 1690d09e41aSPaolo Bonzini * firmware for long periods of time. Annoyingly the firmware can return 1700d09e41aSPaolo Bonzini * a range of return codes, hinting at how long we should wait before 1710d09e41aSPaolo Bonzini * retrying. If you don't care for the hint, the macro below is a good 1720d09e41aSPaolo Bonzini * way to check for the long_busy return codes 1730d09e41aSPaolo Bonzini */ 1740d09e41aSPaolo Bonzini #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 1750d09e41aSPaolo Bonzini && (x <= H_LONG_BUSY_END_RANGE)) 1760d09e41aSPaolo Bonzini 1770d09e41aSPaolo Bonzini /* Flags */ 1780d09e41aSPaolo Bonzini #define H_LARGE_PAGE (1ULL<<(63-16)) 1790d09e41aSPaolo Bonzini #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 1800d09e41aSPaolo Bonzini #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 1810d09e41aSPaolo Bonzini #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 1820d09e41aSPaolo Bonzini #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 1830d09e41aSPaolo Bonzini #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 1840d09e41aSPaolo Bonzini #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 1850d09e41aSPaolo Bonzini #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 1860d09e41aSPaolo Bonzini #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 1870d09e41aSPaolo Bonzini #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 1880d09e41aSPaolo Bonzini #define H_ANDCOND (1ULL<<(63-33)) 1890d09e41aSPaolo Bonzini #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 1900d09e41aSPaolo Bonzini #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 1910d09e41aSPaolo Bonzini #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 1920d09e41aSPaolo Bonzini #define H_COPY_PAGE (1ULL<<(63-49)) 1930d09e41aSPaolo Bonzini #define H_N (1ULL<<(63-61)) 1940d09e41aSPaolo Bonzini #define H_PP1 (1ULL<<(63-62)) 1950d09e41aSPaolo Bonzini #define H_PP2 (1ULL<<(63-63)) 1960d09e41aSPaolo Bonzini 197a46622fdSAlexey Kardashevskiy /* Values for 2nd argument to H_SET_MODE */ 198a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_CIABR 1 199a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_SET_DAWR 2 200a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 201a46622fdSAlexey Kardashevskiy #define H_SET_MODE_RESOURCE_LE 4 202a46622fdSAlexey Kardashevskiy 203a46622fdSAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_LE */ 20442561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_BIG 0 20542561bf2SAnton Blanchard #define H_SET_MODE_ENDIAN_LITTLE 1 20642561bf2SAnton Blanchard 207d5ac4f54SAlexey Kardashevskiy /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 208d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_NONE 0 209d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_0001_8000 2 210d5ac4f54SAlexey Kardashevskiy #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 211d5ac4f54SAlexey Kardashevskiy 2120d09e41aSPaolo Bonzini /* VASI States */ 2130d09e41aSPaolo Bonzini #define H_VASI_INVALID 0 2140d09e41aSPaolo Bonzini #define H_VASI_ENABLED 1 2150d09e41aSPaolo Bonzini #define H_VASI_ABORTED 2 2160d09e41aSPaolo Bonzini #define H_VASI_SUSPENDING 3 2170d09e41aSPaolo Bonzini #define H_VASI_SUSPENDED 4 2180d09e41aSPaolo Bonzini #define H_VASI_RESUMED 5 2190d09e41aSPaolo Bonzini #define H_VASI_COMPLETED 6 2200d09e41aSPaolo Bonzini 2210d09e41aSPaolo Bonzini /* DABRX flags */ 2220d09e41aSPaolo Bonzini #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 2230d09e41aSPaolo Bonzini #define H_DABRX_KERNEL (1ULL<<(63-62)) 2240d09e41aSPaolo Bonzini #define H_DABRX_USER (1ULL<<(63-63)) 2250d09e41aSPaolo Bonzini 2260d09e41aSPaolo Bonzini /* Each control block has to be on a 4K boundary */ 2270d09e41aSPaolo Bonzini #define H_CB_ALIGNMENT 4096 2280d09e41aSPaolo Bonzini 2290d09e41aSPaolo Bonzini /* pSeries hypervisor opcodes */ 2300d09e41aSPaolo Bonzini #define H_REMOVE 0x04 2310d09e41aSPaolo Bonzini #define H_ENTER 0x08 2320d09e41aSPaolo Bonzini #define H_READ 0x0c 2330d09e41aSPaolo Bonzini #define H_CLEAR_MOD 0x10 2340d09e41aSPaolo Bonzini #define H_CLEAR_REF 0x14 2350d09e41aSPaolo Bonzini #define H_PROTECT 0x18 2360d09e41aSPaolo Bonzini #define H_GET_TCE 0x1c 2370d09e41aSPaolo Bonzini #define H_PUT_TCE 0x20 2380d09e41aSPaolo Bonzini #define H_SET_SPRG0 0x24 2390d09e41aSPaolo Bonzini #define H_SET_DABR 0x28 2400d09e41aSPaolo Bonzini #define H_PAGE_INIT 0x2c 2410d09e41aSPaolo Bonzini #define H_SET_ASR 0x30 2420d09e41aSPaolo Bonzini #define H_ASR_ON 0x34 2430d09e41aSPaolo Bonzini #define H_ASR_OFF 0x38 2440d09e41aSPaolo Bonzini #define H_LOGICAL_CI_LOAD 0x3c 2450d09e41aSPaolo Bonzini #define H_LOGICAL_CI_STORE 0x40 2460d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_LOAD 0x44 2470d09e41aSPaolo Bonzini #define H_LOGICAL_CACHE_STORE 0x48 2480d09e41aSPaolo Bonzini #define H_LOGICAL_ICBI 0x4c 2490d09e41aSPaolo Bonzini #define H_LOGICAL_DCBF 0x50 2500d09e41aSPaolo Bonzini #define H_GET_TERM_CHAR 0x54 2510d09e41aSPaolo Bonzini #define H_PUT_TERM_CHAR 0x58 2520d09e41aSPaolo Bonzini #define H_REAL_TO_LOGICAL 0x5c 2530d09e41aSPaolo Bonzini #define H_HYPERVISOR_DATA 0x60 2540d09e41aSPaolo Bonzini #define H_EOI 0x64 2550d09e41aSPaolo Bonzini #define H_CPPR 0x68 2560d09e41aSPaolo Bonzini #define H_IPI 0x6c 2570d09e41aSPaolo Bonzini #define H_IPOLL 0x70 2580d09e41aSPaolo Bonzini #define H_XIRR 0x74 2590d09e41aSPaolo Bonzini #define H_PERFMON 0x7c 2600d09e41aSPaolo Bonzini #define H_MIGRATE_DMA 0x78 2610d09e41aSPaolo Bonzini #define H_REGISTER_VPA 0xDC 2620d09e41aSPaolo Bonzini #define H_CEDE 0xE0 2630d09e41aSPaolo Bonzini #define H_CONFER 0xE4 2640d09e41aSPaolo Bonzini #define H_PROD 0xE8 2650d09e41aSPaolo Bonzini #define H_GET_PPP 0xEC 2660d09e41aSPaolo Bonzini #define H_SET_PPP 0xF0 2670d09e41aSPaolo Bonzini #define H_PURR 0xF4 2680d09e41aSPaolo Bonzini #define H_PIC 0xF8 2690d09e41aSPaolo Bonzini #define H_REG_CRQ 0xFC 2700d09e41aSPaolo Bonzini #define H_FREE_CRQ 0x100 2710d09e41aSPaolo Bonzini #define H_VIO_SIGNAL 0x104 2720d09e41aSPaolo Bonzini #define H_SEND_CRQ 0x108 2730d09e41aSPaolo Bonzini #define H_COPY_RDMA 0x110 2740d09e41aSPaolo Bonzini #define H_REGISTER_LOGICAL_LAN 0x114 2750d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN 0x118 2760d09e41aSPaolo Bonzini #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 2770d09e41aSPaolo Bonzini #define H_SEND_LOGICAL_LAN 0x120 2780d09e41aSPaolo Bonzini #define H_BULK_REMOVE 0x124 2790d09e41aSPaolo Bonzini #define H_MULTICAST_CTRL 0x130 2800d09e41aSPaolo Bonzini #define H_SET_XDABR 0x134 2810d09e41aSPaolo Bonzini #define H_STUFF_TCE 0x138 2820d09e41aSPaolo Bonzini #define H_PUT_TCE_INDIRECT 0x13C 2830d09e41aSPaolo Bonzini #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 2840d09e41aSPaolo Bonzini #define H_VTERM_PARTNER_INFO 0x150 2850d09e41aSPaolo Bonzini #define H_REGISTER_VTERM 0x154 2860d09e41aSPaolo Bonzini #define H_FREE_VTERM 0x158 2870d09e41aSPaolo Bonzini #define H_RESET_EVENTS 0x15C 2880d09e41aSPaolo Bonzini #define H_ALLOC_RESOURCE 0x160 2890d09e41aSPaolo Bonzini #define H_FREE_RESOURCE 0x164 2900d09e41aSPaolo Bonzini #define H_MODIFY_QP 0x168 2910d09e41aSPaolo Bonzini #define H_QUERY_QP 0x16C 2920d09e41aSPaolo Bonzini #define H_REREGISTER_PMR 0x170 2930d09e41aSPaolo Bonzini #define H_REGISTER_SMR 0x174 2940d09e41aSPaolo Bonzini #define H_QUERY_MR 0x178 2950d09e41aSPaolo Bonzini #define H_QUERY_MW 0x17C 2960d09e41aSPaolo Bonzini #define H_QUERY_HCA 0x180 2970d09e41aSPaolo Bonzini #define H_QUERY_PORT 0x184 2980d09e41aSPaolo Bonzini #define H_MODIFY_PORT 0x188 2990d09e41aSPaolo Bonzini #define H_DEFINE_AQP1 0x18C 3000d09e41aSPaolo Bonzini #define H_GET_TRACE_BUFFER 0x190 3010d09e41aSPaolo Bonzini #define H_DEFINE_AQP0 0x194 3020d09e41aSPaolo Bonzini #define H_RESIZE_MR 0x198 3030d09e41aSPaolo Bonzini #define H_ATTACH_MCQP 0x19C 3040d09e41aSPaolo Bonzini #define H_DETACH_MCQP 0x1A0 3050d09e41aSPaolo Bonzini #define H_CREATE_RPT 0x1A4 3060d09e41aSPaolo Bonzini #define H_REMOVE_RPT 0x1A8 3070d09e41aSPaolo Bonzini #define H_REGISTER_RPAGES 0x1AC 3080d09e41aSPaolo Bonzini #define H_DISABLE_AND_GETC 0x1B0 3090d09e41aSPaolo Bonzini #define H_ERROR_DATA 0x1B4 3100d09e41aSPaolo Bonzini #define H_GET_HCA_INFO 0x1B8 3110d09e41aSPaolo Bonzini #define H_GET_PERF_COUNT 0x1BC 3120d09e41aSPaolo Bonzini #define H_MANAGE_TRACE 0x1C0 3130d09e41aSPaolo Bonzini #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 3140d09e41aSPaolo Bonzini #define H_QUERY_INT_STATE 0x1E4 3150d09e41aSPaolo Bonzini #define H_POLL_PENDING 0x1D8 3160d09e41aSPaolo Bonzini #define H_ILLAN_ATTRIBUTES 0x244 3170d09e41aSPaolo Bonzini #define H_MODIFY_HEA_QP 0x250 3180d09e41aSPaolo Bonzini #define H_QUERY_HEA_QP 0x254 3190d09e41aSPaolo Bonzini #define H_QUERY_HEA 0x258 3200d09e41aSPaolo Bonzini #define H_QUERY_HEA_PORT 0x25C 3210d09e41aSPaolo Bonzini #define H_MODIFY_HEA_PORT 0x260 3220d09e41aSPaolo Bonzini #define H_REG_BCMC 0x264 3230d09e41aSPaolo Bonzini #define H_DEREG_BCMC 0x268 3240d09e41aSPaolo Bonzini #define H_REGISTER_HEA_RPAGES 0x26C 3250d09e41aSPaolo Bonzini #define H_DISABLE_AND_GET_HEA 0x270 3260d09e41aSPaolo Bonzini #define H_GET_HEA_INFO 0x274 3270d09e41aSPaolo Bonzini #define H_ALLOC_HEA_RESOURCE 0x278 3280d09e41aSPaolo Bonzini #define H_ADD_CONN 0x284 3290d09e41aSPaolo Bonzini #define H_DEL_CONN 0x288 3300d09e41aSPaolo Bonzini #define H_JOIN 0x298 3310d09e41aSPaolo Bonzini #define H_VASI_STATE 0x2A4 3320d09e41aSPaolo Bonzini #define H_ENABLE_CRQ 0x2B0 3330d09e41aSPaolo Bonzini #define H_GET_EM_PARMS 0x2B8 3340d09e41aSPaolo Bonzini #define H_SET_MPP 0x2D0 3350d09e41aSPaolo Bonzini #define H_GET_MPP 0x2D4 3365d87e4b7SBenjamin Herrenschmidt #define H_XIRR_X 0x2FC 33742561bf2SAnton Blanchard #define H_SET_MODE 0x31C 33842561bf2SAnton Blanchard #define MAX_HCALL_OPCODE H_SET_MODE 3390d09e41aSPaolo Bonzini 3400d09e41aSPaolo Bonzini /* The hcalls above are standardized in PAPR and implemented by pHyp 3410d09e41aSPaolo Bonzini * as well. 3420d09e41aSPaolo Bonzini * 3430d09e41aSPaolo Bonzini * We also need some hcalls which are specific to qemu / KVM-on-POWER. 3440d09e41aSPaolo Bonzini * So far we just need one for H_RTAS, but in future we'll need more 3450d09e41aSPaolo Bonzini * for extensions like virtio. We put those into the 0xf000-0xfffc 3460d09e41aSPaolo Bonzini * range which is reserved by PAPR for "platform-specific" hcalls. 3470d09e41aSPaolo Bonzini */ 3480d09e41aSPaolo Bonzini #define KVMPPC_HCALL_BASE 0xf000 3490d09e41aSPaolo Bonzini #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 3500d09e41aSPaolo Bonzini #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 3512a6593cbSAlexey Kardashevskiy /* Client Architecture support */ 3522a6593cbSAlexey Kardashevskiy #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 3532a6593cbSAlexey Kardashevskiy #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 3540d09e41aSPaolo Bonzini 3552a6593cbSAlexey Kardashevskiy typedef struct sPAPRDeviceTreeUpdateHeader { 3562a6593cbSAlexey Kardashevskiy uint32_t version_id; 3572a6593cbSAlexey Kardashevskiy } sPAPRDeviceTreeUpdateHeader; 3582a6593cbSAlexey Kardashevskiy 3590d09e41aSPaolo Bonzini #define hcall_dprintf(fmt, ...) \ 360aaf87c66SThomas Huth do { \ 361aaf87c66SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 362aaf87c66SThomas Huth } while (0) 3630d09e41aSPaolo Bonzini 36428e02042SDavid Gibson typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 3650d09e41aSPaolo Bonzini target_ulong opcode, 3660d09e41aSPaolo Bonzini target_ulong *args); 3670d09e41aSPaolo Bonzini 3680d09e41aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 3690d09e41aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 3700d09e41aSPaolo Bonzini target_ulong *args); 3710d09e41aSPaolo Bonzini 3720d09e41aSPaolo Bonzini int spapr_allocate_irq(int hint, bool lsi); 373f1c2dc7cSAlexey Kardashevskiy int spapr_allocate_irq_block(int num, bool lsi, bool msi); 3740d09e41aSPaolo Bonzini 375ee954280SGavin Shan /* ibm,set-eeh-option */ 376ee954280SGavin Shan #define RTAS_EEH_DISABLE 0 377ee954280SGavin Shan #define RTAS_EEH_ENABLE 1 378ee954280SGavin Shan #define RTAS_EEH_THAW_IO 2 379ee954280SGavin Shan #define RTAS_EEH_THAW_DMA 3 380ee954280SGavin Shan 381ee954280SGavin Shan /* ibm,get-config-addr-info2 */ 382ee954280SGavin Shan #define RTAS_GET_PE_ADDR 0 383ee954280SGavin Shan #define RTAS_GET_PE_MODE 1 384ee954280SGavin Shan #define RTAS_PE_MODE_NONE 0 385ee954280SGavin Shan #define RTAS_PE_MODE_NOT_SHARED 1 386ee954280SGavin Shan #define RTAS_PE_MODE_SHARED 2 387ee954280SGavin Shan 388ee954280SGavin Shan /* ibm,read-slot-reset-state2 */ 389ee954280SGavin Shan #define RTAS_EEH_PE_STATE_NORMAL 0 390ee954280SGavin Shan #define RTAS_EEH_PE_STATE_RESET 1 391ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 392ee954280SGavin Shan #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 393ee954280SGavin Shan #define RTAS_EEH_PE_STATE_UNAVAIL 5 394ee954280SGavin Shan #define RTAS_EEH_NOT_SUPPORT 0 395ee954280SGavin Shan #define RTAS_EEH_SUPPORT 1 396ee954280SGavin Shan #define RTAS_EEH_PE_UNAVAIL_INFO 1000 397ee954280SGavin Shan #define RTAS_EEH_PE_RECOVER_INFO 0 398ee954280SGavin Shan 399ee954280SGavin Shan /* ibm,set-slot-reset */ 400ee954280SGavin Shan #define RTAS_SLOT_RESET_DEACTIVATE 0 401ee954280SGavin Shan #define RTAS_SLOT_RESET_HOT 1 402ee954280SGavin Shan #define RTAS_SLOT_RESET_FUNDAMENTAL 3 403ee954280SGavin Shan 404ee954280SGavin Shan /* ibm,slot-error-detail */ 405ee954280SGavin Shan #define RTAS_SLOT_TEMP_ERR_LOG 1 406ee954280SGavin Shan #define RTAS_SLOT_PERM_ERR_LOG 2 407ee954280SGavin Shan 408a64d325dSAlexey Kardashevskiy /* RTAS return codes */ 409a64d325dSAlexey Kardashevskiy #define RTAS_OUT_SUCCESS 0 410a64d325dSAlexey Kardashevskiy #define RTAS_OUT_NO_ERRORS_FOUND 1 411a64d325dSAlexey Kardashevskiy #define RTAS_OUT_HW_ERROR -1 412a64d325dSAlexey Kardashevskiy #define RTAS_OUT_BUSY -2 413a64d325dSAlexey Kardashevskiy #define RTAS_OUT_PARAM_ERROR -3 4143ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_SUPPORTED -3 4159d1852ceSMichael Roth #define RTAS_OUT_NO_SUCH_INDICATOR -3 4163ada6b11SAlexey Kardashevskiy #define RTAS_OUT_NOT_AUTHORIZED -9002 417a64d325dSAlexey Kardashevskiy 4183a3b8502SAlexey Kardashevskiy /* RTAS tokens */ 4193a3b8502SAlexey Kardashevskiy #define RTAS_TOKEN_BASE 0x2000 4203a3b8502SAlexey Kardashevskiy 4213a3b8502SAlexey Kardashevskiy #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 4223a3b8502SAlexey Kardashevskiy #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 4233a3b8502SAlexey Kardashevskiy #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 4243a3b8502SAlexey Kardashevskiy #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 4253a3b8502SAlexey Kardashevskiy #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 4263a3b8502SAlexey Kardashevskiy #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 4273a3b8502SAlexey Kardashevskiy #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 4283a3b8502SAlexey Kardashevskiy #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 4293a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 4303a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 4313a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 4323a3b8502SAlexey Kardashevskiy #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 4333a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 4343a3b8502SAlexey Kardashevskiy #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 4353a3b8502SAlexey Kardashevskiy #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 4363a3b8502SAlexey Kardashevskiy #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 4373a3b8502SAlexey Kardashevskiy #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 4383a3b8502SAlexey Kardashevskiy #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 4393a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 4403a3b8502SAlexey Kardashevskiy #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 4413a3b8502SAlexey Kardashevskiy #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 4423a3b8502SAlexey Kardashevskiy #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 4433a3b8502SAlexey Kardashevskiy #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 4443a3b8502SAlexey Kardashevskiy #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 4453a3b8502SAlexey Kardashevskiy #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 4463a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 4473a3b8502SAlexey Kardashevskiy #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 4483a3b8502SAlexey Kardashevskiy #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 4493a3b8502SAlexey Kardashevskiy #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 4503a3b8502SAlexey Kardashevskiy #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 4513a3b8502SAlexey Kardashevskiy #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 4523a3b8502SAlexey Kardashevskiy #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 453ee954280SGavin Shan #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 454ee954280SGavin Shan #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 455ee954280SGavin Shan #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 456ee954280SGavin Shan #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 457ee954280SGavin Shan #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 458ee954280SGavin Shan #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 4593a3b8502SAlexey Kardashevskiy 460ee954280SGavin Shan #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) 4613a3b8502SAlexey Kardashevskiy 4623052d951SSam bobroff /* RTAS ibm,get-system-parameter token values */ 4633b50d897SSam bobroff #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 4643052d951SSam bobroff #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 465b907d7b0SSam bobroff #define RTAS_SYSPARM_UUID 48 4663052d951SSam bobroff 4678c8639dfSMike Day /* RTAS indicator/sensor types 4688c8639dfSMike Day * 4698c8639dfSMike Day * as defined by PAPR+ 2.7 7.3.5.4, Table 41 4708c8639dfSMike Day * 4718c8639dfSMike Day * NOTE: currently only DR-related sensors are implemented here 4728c8639dfSMike Day */ 4738c8639dfSMike Day #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 4748c8639dfSMike Day #define RTAS_SENSOR_TYPE_DR 9002 4758c8639dfSMike Day #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 4768c8639dfSMike Day #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 4778c8639dfSMike Day 4783052d951SSam bobroff /* Possible values for the platform-processor-diagnostics-run-mode parameter 4793052d951SSam bobroff * of the RTAS ibm,get-system-parameter call. 4803052d951SSam bobroff */ 4813052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_DISABLED 0 4823052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 4833052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 4843052d951SSam bobroff #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 4853052d951SSam bobroff 4864fe822e0SAlexey Kardashevskiy static inline uint64_t ppc64_phys_to_real(uint64_t addr) 4874fe822e0SAlexey Kardashevskiy { 4884fe822e0SAlexey Kardashevskiy return addr & ~0xF000000000000000ULL; 4894fe822e0SAlexey Kardashevskiy } 4904fe822e0SAlexey Kardashevskiy 4910d09e41aSPaolo Bonzini static inline uint32_t rtas_ld(target_ulong phys, int n) 4920d09e41aSPaolo Bonzini { 493fdfba1a2SEdgar E. Iglesias return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 4940d09e41aSPaolo Bonzini } 4950d09e41aSPaolo Bonzini 496a14aa92bSGavin Shan static inline uint64_t rtas_ldq(target_ulong phys, int n) 497a14aa92bSGavin Shan { 498a14aa92bSGavin Shan return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 499a14aa92bSGavin Shan } 500a14aa92bSGavin Shan 5010d09e41aSPaolo Bonzini static inline void rtas_st(target_ulong phys, int n, uint32_t val) 5020d09e41aSPaolo Bonzini { 503ab1da857SEdgar E. Iglesias stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 5040d09e41aSPaolo Bonzini } 5050d09e41aSPaolo Bonzini 506ab316865SMichael Roth static inline void rtas_st_buffer_direct(target_ulong phys, 507ab316865SMichael Roth target_ulong phys_len, 508ab316865SMichael Roth uint8_t *buffer, uint16_t buffer_len) 509ab316865SMichael Roth { 510ab316865SMichael Roth cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer, 511ab316865SMichael Roth MIN(buffer_len, phys_len)); 512ab316865SMichael Roth } 513ce3fa1ecSSam bobroff 514ce3fa1ecSSam bobroff static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, 515ce3fa1ecSSam bobroff uint8_t *buffer, uint16_t buffer_len) 516ce3fa1ecSSam bobroff { 517ce3fa1ecSSam bobroff if (phys_len < 2) { 518ce3fa1ecSSam bobroff return; 519ce3fa1ecSSam bobroff } 520ce3fa1ecSSam bobroff stw_be_phys(&address_space_memory, 521ce3fa1ecSSam bobroff ppc64_phys_to_real(phys), buffer_len); 522ab316865SMichael Roth rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len); 523ce3fa1ecSSam bobroff } 524ce3fa1ecSSam bobroff 52528e02042SDavid Gibson typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 526210b580bSAnthony Liguori uint32_t token, 5270d09e41aSPaolo Bonzini uint32_t nargs, target_ulong args, 5280d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 5293a3b8502SAlexey Kardashevskiy void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 53028e02042SDavid Gibson target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 5310d09e41aSPaolo Bonzini uint32_t token, uint32_t nargs, target_ulong args, 5320d09e41aSPaolo Bonzini uint32_t nret, target_ulong rets); 5330d09e41aSPaolo Bonzini int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 5340d09e41aSPaolo Bonzini hwaddr rtas_size); 5350d09e41aSPaolo Bonzini 5360d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SHIFT 12 5370d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 5380d09e41aSPaolo Bonzini #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 5390d09e41aSPaolo Bonzini 5400d09e41aSPaolo Bonzini #define SPAPR_VIO_BASE_LIOBN 0x00000000 5414290ca49SAlexey Kardashevskiy #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 542c8545818SAlexey Kardashevskiy #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 543c8545818SAlexey Kardashevskiy (0x80000000 | ((phb_index) << 8) | (window_num)) 544d9d96a3cSAlexey Kardashevskiy #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 545c8545818SAlexey Kardashevskiy #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 5460d09e41aSPaolo Bonzini 5470d09e41aSPaolo Bonzini #define RTAS_ERROR_LOG_MAX 2048 5480d09e41aSPaolo Bonzini 54979853e18STyrel Datwyler #define RTAS_EVENT_SCAN_RATE 1 55079853e18STyrel Datwyler 5512b7dc949SPaolo Bonzini typedef struct sPAPRTCETable sPAPRTCETable; 5520d09e41aSPaolo Bonzini 553a83000f5SAnthony Liguori #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 554a83000f5SAnthony Liguori #define SPAPR_TCE_TABLE(obj) \ 555a83000f5SAnthony Liguori OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 556a83000f5SAnthony Liguori 557a83000f5SAnthony Liguori struct sPAPRTCETable { 558a83000f5SAnthony Liguori DeviceState parent; 559a83000f5SAnthony Liguori uint32_t liobn; 560a83000f5SAnthony Liguori uint32_t nb_table; 5611b8eceeeSAlexey Kardashevskiy uint64_t bus_offset; 562650f33adSAlexey Kardashevskiy uint32_t page_shift; 563a83000f5SAnthony Liguori uint64_t *table; 564a83000f5SAnthony Liguori bool bypass; 5659bb62a07SAlexey Kardashevskiy bool vfio_accel; 566a83000f5SAnthony Liguori int fd; 567a83000f5SAnthony Liguori MemoryRegion iommu; 568ee9a569aSAlexey Kardashevskiy struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 569a83000f5SAnthony Liguori QLIST_ENTRY(sPAPRTCETable) list; 570a83000f5SAnthony Liguori }; 571a83000f5SAnthony Liguori 572f9ce8e0aSThomas Huth sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 57331fe14d1SNathan Fontenot 57431fe14d1SNathan Fontenot struct sPAPREventLogEntry { 57531fe14d1SNathan Fontenot int log_type; 57679853e18STyrel Datwyler bool exception; 57731fe14d1SNathan Fontenot void *data; 57831fe14d1SNathan Fontenot QTAILQ_ENTRY(sPAPREventLogEntry) next; 57931fe14d1SNathan Fontenot }; 58031fe14d1SNathan Fontenot 58128e02042SDavid Gibson void spapr_events_init(sPAPRMachineState *sm); 5820d09e41aSPaolo Bonzini void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 58328e02042SDavid Gibson int spapr_h_cas_compose_response(sPAPRMachineState *sm, 584*03d196b7SBharata B Rao target_ulong addr, target_ulong size, 585*03d196b7SBharata B Rao bool cpu_update, bool memory_update); 58684af6d9fSPaolo Bonzini sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 5871b8eceeeSAlexey Kardashevskiy uint64_t bus_offset, 588650f33adSAlexey Kardashevskiy uint32_t page_shift, 5899bb62a07SAlexey Kardashevskiy uint32_t nb_table, 5909bb62a07SAlexey Kardashevskiy bool vfio_accel); 591a84bb436SPaolo Bonzini MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 5920d09e41aSPaolo Bonzini int spapr_dma_dt(void *fdt, int node_off, const char *propname, 5930d09e41aSPaolo Bonzini uint32_t liobn, uint64_t window, uint32_t size); 5940d09e41aSPaolo Bonzini int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 5952b7dc949SPaolo Bonzini sPAPRTCETable *tcet); 596eefaccc0SDavid Gibson void spapr_pci_switch_vga(bool big_endian); 59731fe14d1SNathan Fontenot void spapr_hotplug_req_add_event(sPAPRDRConnector *drc); 59831fe14d1SNathan Fontenot void spapr_hotplug_req_remove_event(sPAPRDRConnector *drc); 59928df36a1SDavid Gibson 60046503c2bSMichael Roth /* rtas-configure-connector state */ 60146503c2bSMichael Roth struct sPAPRConfigureConnectorState { 60246503c2bSMichael Roth uint32_t drc_index; 60346503c2bSMichael Roth int fdt_offset; 60446503c2bSMichael Roth int fdt_depth; 60546503c2bSMichael Roth QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 60646503c2bSMichael Roth }; 60746503c2bSMichael Roth 60846503c2bSMichael Roth void spapr_ccs_reset_hook(void *opaque); 60946503c2bSMichael Roth 61028df36a1SDavid Gibson #define TYPE_SPAPR_RTC "spapr-rtc" 61128df36a1SDavid Gibson 61228df36a1SDavid Gibson void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 613880ae7deSDavid Gibson int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 6140d09e41aSPaolo Bonzini 615db4ef288SBharata B Rao #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 616db4ef288SBharata B Rao 6174a1c9cf0SBharata B Rao /* 6184a1c9cf0SBharata B Rao * This defines the maximum number of DIMM slots we can have for sPAPR 6194a1c9cf0SBharata B Rao * guest. This is not defined by sPAPR but we are defining it to 32 slots 6204a1c9cf0SBharata B Rao * based on default number of slots provided by PowerPC kernel. 6214a1c9cf0SBharata B Rao */ 6224a1c9cf0SBharata B Rao #define SPAPR_MAX_RAM_SLOTS 32 6234a1c9cf0SBharata B Rao 6244a1c9cf0SBharata B Rao /* 1GB alignment for hotplug memory region */ 6254a1c9cf0SBharata B Rao #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 6264a1c9cf0SBharata B Rao 627*03d196b7SBharata B Rao /* 628*03d196b7SBharata B Rao * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 629*03d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 630*03d196b7SBharata B Rao */ 631*03d196b7SBharata B Rao #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 632*03d196b7SBharata B Rao 633*03d196b7SBharata B Rao /* 634*03d196b7SBharata B Rao * This flag value defines the LMB as assigned in ibm,dynamic-memory 635*03d196b7SBharata B Rao * property under ibm,dynamic-reconfiguration-memory node. 636*03d196b7SBharata B Rao */ 637*03d196b7SBharata B Rao #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 638*03d196b7SBharata B Rao 6390d09e41aSPaolo Bonzini #endif /* !defined (__HW_SPAPR_H__) */ 640