1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 typedef struct { 33 MemoryRegion ram; 34 MemoryRegion container; /* used for clipping */ 35 hwaddr base; 36 hwaddr size; 37 uint32_t bcr; 38 } Ppc4xxSdramBank; 39 40 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 41 Ppc4xxSdramBank ram_banks[], 42 const ram_addr_t sdram_bank_sizes[]); 43 44 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" 45 46 /* 47 * Generic DCR device 48 */ 49 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 50 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 51 struct Ppc4xxDcrDeviceState { 52 SysBusDevice parent_obj; 53 54 PowerPCCPU *cpu; 55 }; 56 57 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 58 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 59 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 60 Error **errp); 61 62 /* Memory Access Layer (MAL) */ 63 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 64 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 65 struct Ppc4xxMalState { 66 Ppc4xxDcrDeviceState parent_obj; 67 68 qemu_irq irqs[4]; 69 uint32_t cfg; 70 uint32_t esr; 71 uint32_t ier; 72 uint32_t txcasr; 73 uint32_t txcarr; 74 uint32_t txeobisr; 75 uint32_t txdeir; 76 uint32_t rxcasr; 77 uint32_t rxcarr; 78 uint32_t rxeobisr; 79 uint32_t rxdeir; 80 uint32_t *txctpr; 81 uint32_t *rxctpr; 82 uint32_t *rcbs; 83 uint8_t txcnum; 84 uint8_t rxcnum; 85 }; 86 87 /* Peripheral local bus arbitrer */ 88 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 89 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 90 struct Ppc4xxPlbState { 91 Ppc4xxDcrDeviceState parent_obj; 92 93 uint32_t acr; 94 uint32_t bear; 95 uint32_t besr; 96 }; 97 98 /* Peripheral controller */ 99 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 100 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 101 struct Ppc4xxEbcState { 102 Ppc4xxDcrDeviceState parent_obj; 103 104 uint32_t addr; 105 uint32_t bcr[8]; 106 uint32_t bap[8]; 107 uint32_t bear; 108 uint32_t besr0; 109 uint32_t besr1; 110 uint32_t cfg; 111 }; 112 113 /* SDRAM DDR controller */ 114 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 115 #define SDR0_DDR0_DDRM_DDR1 0x20000000 116 #define SDR0_DDR0_DDRM_DDR2 0x40000000 117 118 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" 119 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); 120 struct Ppc4xxSdramDdrState { 121 Ppc4xxDcrDeviceState parent_obj; 122 123 MemoryRegion *dram_mr; 124 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 125 Ppc4xxSdramBank bank[4]; 126 qemu_irq irq; 127 128 uint32_t addr; 129 uint32_t besr0; 130 uint32_t besr1; 131 uint32_t bear; 132 uint32_t cfg; 133 uint32_t status; 134 uint32_t rtr; 135 uint32_t pmit; 136 uint32_t tr; 137 uint32_t ecccfg; 138 uint32_t eccesr; 139 }; 140 141 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s); 142 143 /* SDRAM DDR2 controller */ 144 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" 145 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); 146 struct Ppc4xxSdramDdr2State { 147 Ppc4xxDcrDeviceState parent_obj; 148 149 MemoryRegion *dram_mr; 150 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 151 Ppc4xxSdramBank bank[4]; 152 153 uint32_t addr; 154 uint32_t mcopt2; 155 }; 156 157 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s); 158 159 #endif /* PPC4XX_H */ 160