1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 #define TYPE_PPC4xx_HOST_BRIDGE "ppc4xx-host-bridge" 33 #define TYPE_PPC4xx_PCI_HOST "ppc4xx-pci-host" 34 #define TYPE_PPC440_PCIX_HOST "ppc440-pcix-host" 35 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 36 37 /* 38 * Generic DCR device 39 */ 40 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 41 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 42 struct Ppc4xxDcrDeviceState { 43 SysBusDevice parent_obj; 44 45 PowerPCCPU *cpu; 46 }; 47 48 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 49 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 50 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 51 Error **errp); 52 53 /* Memory Access Layer (MAL) */ 54 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 55 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 56 struct Ppc4xxMalState { 57 Ppc4xxDcrDeviceState parent_obj; 58 59 qemu_irq irqs[4]; 60 uint32_t cfg; 61 uint32_t esr; 62 uint32_t ier; 63 uint32_t txcasr; 64 uint32_t txcarr; 65 uint32_t txeobisr; 66 uint32_t txdeir; 67 uint32_t rxcasr; 68 uint32_t rxcarr; 69 uint32_t rxeobisr; 70 uint32_t rxdeir; 71 uint32_t *txctpr; 72 uint32_t *rxctpr; 73 uint32_t *rcbs; 74 uint8_t txcnum; 75 uint8_t rxcnum; 76 }; 77 78 /* Peripheral local bus arbitrer */ 79 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 80 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 81 struct Ppc4xxPlbState { 82 Ppc4xxDcrDeviceState parent_obj; 83 84 uint32_t acr; 85 uint32_t bear; 86 uint32_t besr; 87 }; 88 89 /* Peripheral controller */ 90 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 91 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 92 struct Ppc4xxEbcState { 93 Ppc4xxDcrDeviceState parent_obj; 94 95 uint32_t addr; 96 uint32_t bcr[8]; 97 uint32_t bap[8]; 98 uint32_t bear; 99 uint32_t besr0; 100 uint32_t besr1; 101 uint32_t cfg; 102 }; 103 104 /* SDRAM DDR controller */ 105 typedef struct { 106 MemoryRegion ram; 107 MemoryRegion container; /* used for clipping */ 108 hwaddr base; 109 hwaddr size; 110 uint32_t bcr; 111 } Ppc4xxSdramBank; 112 113 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 114 #define SDR0_DDR0_DDRM_DDR1 0x20000000 115 #define SDR0_DDR0_DDRM_DDR2 0x40000000 116 117 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" 118 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); 119 struct Ppc4xxSdramDdrState { 120 Ppc4xxDcrDeviceState parent_obj; 121 122 MemoryRegion *dram_mr; 123 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 124 Ppc4xxSdramBank bank[4]; 125 qemu_irq irq; 126 127 uint32_t addr; 128 uint32_t besr0; 129 uint32_t besr1; 130 uint32_t bear; 131 uint32_t cfg; 132 uint32_t status; 133 uint32_t rtr; 134 uint32_t pmit; 135 uint32_t tr; 136 uint32_t ecccfg; 137 uint32_t eccesr; 138 }; 139 140 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s); 141 142 /* SDRAM DDR2 controller */ 143 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" 144 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); 145 struct Ppc4xxSdramDdr2State { 146 Ppc4xxDcrDeviceState parent_obj; 147 148 MemoryRegion *dram_mr; 149 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 150 Ppc4xxSdramBank bank[4]; 151 152 uint32_t addr; 153 uint32_t mcopt2; 154 }; 155 156 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s); 157 158 #endif /* PPC4XX_H */ 159