1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 #define TYPE_PPC4xx_HOST_BRIDGE "ppc4xx-host-bridge" 33 #define TYPE_PPC4xx_PCI_HOST "ppc4xx-pci-host" 34 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 35 36 /* 37 * Generic DCR device 38 */ 39 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 40 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 41 struct Ppc4xxDcrDeviceState { 42 SysBusDevice parent_obj; 43 44 PowerPCCPU *cpu; 45 }; 46 47 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 48 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 49 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 50 Error **errp); 51 52 /* Memory Access Layer (MAL) */ 53 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 54 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 55 struct Ppc4xxMalState { 56 Ppc4xxDcrDeviceState parent_obj; 57 58 qemu_irq irqs[4]; 59 uint32_t cfg; 60 uint32_t esr; 61 uint32_t ier; 62 uint32_t txcasr; 63 uint32_t txcarr; 64 uint32_t txeobisr; 65 uint32_t txdeir; 66 uint32_t rxcasr; 67 uint32_t rxcarr; 68 uint32_t rxeobisr; 69 uint32_t rxdeir; 70 uint32_t *txctpr; 71 uint32_t *rxctpr; 72 uint32_t *rcbs; 73 uint8_t txcnum; 74 uint8_t rxcnum; 75 }; 76 77 /* Peripheral local bus arbitrer */ 78 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 79 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 80 struct Ppc4xxPlbState { 81 Ppc4xxDcrDeviceState parent_obj; 82 83 uint32_t acr; 84 uint32_t bear; 85 uint32_t besr; 86 }; 87 88 /* Peripheral controller */ 89 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 90 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 91 struct Ppc4xxEbcState { 92 Ppc4xxDcrDeviceState parent_obj; 93 94 uint32_t addr; 95 uint32_t bcr[8]; 96 uint32_t bap[8]; 97 uint32_t bear; 98 uint32_t besr0; 99 uint32_t besr1; 100 uint32_t cfg; 101 }; 102 103 /* SDRAM DDR controller */ 104 typedef struct { 105 MemoryRegion ram; 106 MemoryRegion container; /* used for clipping */ 107 hwaddr base; 108 hwaddr size; 109 uint32_t bcr; 110 } Ppc4xxSdramBank; 111 112 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 113 #define SDR0_DDR0_DDRM_DDR1 0x20000000 114 #define SDR0_DDR0_DDRM_DDR2 0x40000000 115 116 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" 117 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); 118 struct Ppc4xxSdramDdrState { 119 Ppc4xxDcrDeviceState parent_obj; 120 121 MemoryRegion *dram_mr; 122 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 123 Ppc4xxSdramBank bank[4]; 124 qemu_irq irq; 125 126 uint32_t addr; 127 uint32_t besr0; 128 uint32_t besr1; 129 uint32_t bear; 130 uint32_t cfg; 131 uint32_t status; 132 uint32_t rtr; 133 uint32_t pmit; 134 uint32_t tr; 135 uint32_t ecccfg; 136 uint32_t eccesr; 137 }; 138 139 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s); 140 141 /* SDRAM DDR2 controller */ 142 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" 143 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); 144 struct Ppc4xxSdramDdr2State { 145 Ppc4xxDcrDeviceState parent_obj; 146 147 MemoryRegion *dram_mr; 148 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 149 Ppc4xxSdramBank bank[4]; 150 151 uint32_t addr; 152 uint32_t mcopt2; 153 }; 154 155 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s); 156 157 #endif /* PPC4XX_H */ 158