1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 typedef struct { 33 MemoryRegion ram; 34 MemoryRegion container; /* used for clipping */ 35 hwaddr base; 36 hwaddr size; 37 uint32_t bcr; 38 } Ppc4xxSdramBank; 39 40 void ppc440_sdram_enable(CPUPPCState *env); 41 42 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 43 Ppc4xxSdramBank ram_banks[], 44 const ram_addr_t sdram_bank_sizes[]); 45 46 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" 47 48 /* 49 * Generic DCR device 50 */ 51 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 52 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 53 struct Ppc4xxDcrDeviceState { 54 SysBusDevice parent_obj; 55 56 PowerPCCPU *cpu; 57 }; 58 59 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 60 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 61 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 62 Error **errp); 63 64 /* Memory Access Layer (MAL) */ 65 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 66 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 67 struct Ppc4xxMalState { 68 Ppc4xxDcrDeviceState parent_obj; 69 70 qemu_irq irqs[4]; 71 uint32_t cfg; 72 uint32_t esr; 73 uint32_t ier; 74 uint32_t txcasr; 75 uint32_t txcarr; 76 uint32_t txeobisr; 77 uint32_t txdeir; 78 uint32_t rxcasr; 79 uint32_t rxcarr; 80 uint32_t rxeobisr; 81 uint32_t rxdeir; 82 uint32_t *txctpr; 83 uint32_t *rxctpr; 84 uint32_t *rcbs; 85 uint8_t txcnum; 86 uint8_t rxcnum; 87 }; 88 89 /* Peripheral local bus arbitrer */ 90 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 91 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 92 struct Ppc4xxPlbState { 93 Ppc4xxDcrDeviceState parent_obj; 94 95 uint32_t acr; 96 uint32_t bear; 97 uint32_t besr; 98 }; 99 100 /* Peripheral controller */ 101 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 102 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 103 struct Ppc4xxEbcState { 104 Ppc4xxDcrDeviceState parent_obj; 105 106 uint32_t addr; 107 uint32_t bcr[8]; 108 uint32_t bap[8]; 109 uint32_t bear; 110 uint32_t besr0; 111 uint32_t besr1; 112 uint32_t cfg; 113 }; 114 115 /* SDRAM DDR controller */ 116 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" 117 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); 118 struct Ppc4xxSdramDdrState { 119 Ppc4xxDcrDeviceState parent_obj; 120 121 MemoryRegion *dram_mr; 122 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 123 Ppc4xxSdramBank bank[4]; 124 qemu_irq irq; 125 126 uint32_t addr; 127 uint32_t besr0; 128 uint32_t besr1; 129 uint32_t bear; 130 uint32_t cfg; 131 uint32_t status; 132 uint32_t rtr; 133 uint32_t pmit; 134 uint32_t tr; 135 uint32_t ecccfg; 136 uint32_t eccesr; 137 }; 138 139 void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s); 140 141 #endif /* PPC4XX_H */ 142