1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016-2022, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_LPC_H 21 #define PPC_PNV_LPC_H 22 23 #include "exec/memory.h" 24 #include "hw/ppc/pnv.h" 25 #include "hw/qdev-core.h" 26 27 #define TYPE_PNV_LPC "pnv-lpc" 28 typedef struct PnvLpcClass PnvLpcClass; 29 typedef struct PnvLpcController PnvLpcController; 30 DECLARE_OBJ_CHECKERS(PnvLpcController, PnvLpcClass, 31 PNV_LPC, TYPE_PNV_LPC) 32 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8" 33 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV8_LPC, 34 TYPE_PNV8_LPC) 35 36 #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" 37 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC, 38 TYPE_PNV9_LPC) 39 40 #define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10" 41 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC, 42 TYPE_PNV10_LPC) 43 44 struct PnvLpcController { 45 DeviceState parent; 46 47 uint64_t eccb_stat_reg; 48 uint32_t eccb_data_reg; 49 50 /* OPB bus */ 51 MemoryRegion opb_mr; 52 AddressSpace opb_as; 53 54 /* ISA IO and Memory space */ 55 MemoryRegion isa_io; 56 MemoryRegion isa_mem; 57 MemoryRegion isa_fw; 58 59 /* Windows from OPB to ISA (aliases) */ 60 MemoryRegion opb_isa_io; 61 MemoryRegion opb_isa_mem; 62 MemoryRegion opb_isa_fw; 63 64 /* Registers */ 65 MemoryRegion lpc_hc_regs; 66 MemoryRegion opb_master_regs; 67 68 /* OPB Master LS registers */ 69 uint32_t opb_irq_route0; 70 uint32_t opb_irq_route1; 71 uint32_t opb_irq_stat; 72 uint32_t opb_irq_mask; 73 uint32_t opb_irq_pol; 74 uint32_t opb_irq_input; 75 76 /* LPC HC registers */ 77 uint32_t lpc_hc_fw_seg_idsel; 78 uint32_t lpc_hc_fw_rd_acc_size; 79 uint32_t lpc_hc_irqser_ctrl; 80 uint32_t lpc_hc_irqmask; 81 uint32_t lpc_hc_irqstat; 82 uint32_t lpc_hc_error_addr; 83 84 /* XSCOM registers */ 85 MemoryRegion xscom_regs; 86 87 /* PSI to generate interrupts */ 88 qemu_irq psi_irq; 89 }; 90 91 struct PnvLpcClass { 92 DeviceClass parent_class; 93 94 DeviceRealize parent_realize; 95 }; 96 97 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp); 98 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, 99 uint64_t lpcm_addr, uint64_t lpcm_size); 100 101 #endif /* PPC_PNV_LPC_H */ 102