1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016-2022, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_LPC_H 21 #define PPC_PNV_LPC_H 22 23 #include "qom/object.h" 24 25 #define TYPE_PNV_LPC "pnv-lpc" 26 typedef struct PnvLpcClass PnvLpcClass; 27 typedef struct PnvLpcController PnvLpcController; 28 DECLARE_OBJ_CHECKERS(PnvLpcController, PnvLpcClass, 29 PNV_LPC, TYPE_PNV_LPC) 30 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8" 31 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV8_LPC, 32 TYPE_PNV8_LPC) 33 34 #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" 35 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC, 36 TYPE_PNV9_LPC) 37 38 #define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10" 39 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC, 40 TYPE_PNV10_LPC) 41 42 struct PnvLpcController { 43 DeviceState parent; 44 45 uint64_t eccb_stat_reg; 46 uint32_t eccb_data_reg; 47 48 /* OPB bus */ 49 MemoryRegion opb_mr; 50 AddressSpace opb_as; 51 52 /* ISA IO and Memory space */ 53 MemoryRegion isa_io; 54 MemoryRegion isa_mem; 55 MemoryRegion isa_fw; 56 57 /* Windows from OPB to ISA (aliases) */ 58 MemoryRegion opb_isa_io; 59 MemoryRegion opb_isa_mem; 60 MemoryRegion opb_isa_fw; 61 62 /* Registers */ 63 MemoryRegion lpc_hc_regs; 64 MemoryRegion opb_master_regs; 65 66 /* OPB Master LS registers */ 67 uint32_t opb_irq_route0; 68 uint32_t opb_irq_route1; 69 uint32_t opb_irq_stat; 70 uint32_t opb_irq_mask; 71 uint32_t opb_irq_pol; 72 uint32_t opb_irq_input; 73 74 /* LPC HC registers */ 75 uint32_t lpc_hc_fw_seg_idsel; 76 uint32_t lpc_hc_fw_rd_acc_size; 77 uint32_t lpc_hc_irqser_ctrl; 78 uint32_t lpc_hc_irqmask; 79 uint32_t lpc_hc_irqstat; 80 uint32_t lpc_hc_error_addr; 81 82 /* XSCOM registers */ 83 MemoryRegion xscom_regs; 84 85 /* PSI to generate interrupts */ 86 qemu_irq psi_irq; 87 }; 88 89 struct PnvLpcClass { 90 DeviceClass parent_class; 91 92 DeviceRealize parent_realize; 93 }; 94 95 /* 96 * Old compilers error on typdef forward declarations. Keep them happy. 97 */ 98 struct PnvChip; 99 100 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp); 101 int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, 102 uint64_t lpcm_addr, uint64_t lpcm_size); 103 104 #endif /* PPC_PNV_LPC_H */ 105