1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_adu.h" 6 #include "hw/ppc/pnv_chiptod.h" 7 #include "hw/ppc/pnv_core.h" 8 #include "hw/ppc/pnv_homer.h" 9 #include "hw/ppc/pnv_n1_chiplet.h" 10 #include "hw/ppc/pnv_lpc.h" 11 #include "hw/ppc/pnv_occ.h" 12 #include "hw/ppc/pnv_psi.h" 13 #include "hw/ppc/pnv_sbe.h" 14 #include "hw/ppc/pnv_xive.h" 15 #include "hw/ppc/pnv_i2c.h" 16 #include "hw/sysbus.h" 17 18 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 19 PNV_CHIP) 20 21 struct PnvChip { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 uint32_t chip_id; 27 uint64_t ram_start; 28 uint64_t ram_size; 29 30 bool big_core; 31 uint32_t nr_cores; 32 uint32_t nr_threads; 33 uint64_t cores_mask; 34 PnvCore **cores; 35 36 uint32_t num_pecs; 37 38 MemoryRegion xscom_mmio; 39 MemoryRegion xscom; 40 AddressSpace xscom_as; 41 42 MemoryRegion *fw_mr; 43 gchar *dt_isa_nodename; 44 }; 45 46 #define TYPE_PNV8_CHIP "pnv8-chip" 47 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 48 TYPE_PNV8_CHIP) 49 50 struct Pnv8Chip { 51 /*< private >*/ 52 PnvChip parent_obj; 53 54 /*< public >*/ 55 MemoryRegion icp_mmio; 56 57 PnvLpcController lpc; 58 Pnv8Psi psi; 59 PnvOCC occ; 60 PnvHomer homer; 61 62 #define PNV8_CHIP_PHB3_MAX 4 63 /* 64 * The array is used to allow quick access to the phbs by 65 * pnv_ics_get_child() and pnv_ics_resend_child(). 66 */ 67 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 68 uint32_t num_phbs; 69 70 XICSFabric *xics; 71 }; 72 73 #define TYPE_PNV9_CHIP "pnv9-chip" 74 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 75 TYPE_PNV9_CHIP) 76 77 struct Pnv9Chip { 78 /*< private >*/ 79 PnvChip parent_obj; 80 81 /*< public >*/ 82 PnvADU adu; 83 PnvXive xive; 84 Pnv9Psi psi; 85 PnvLpcController lpc; 86 PnvChipTOD chiptod; 87 PnvOCC occ; 88 PnvSBE sbe; 89 PnvHomer homer; 90 91 uint32_t nr_quads; 92 PnvQuad *quads; 93 94 #define PNV9_CHIP_MAX_PEC 3 95 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 96 97 #define PNV9_CHIP_MAX_I2C 4 98 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 99 }; 100 101 /* 102 * A SMT8 fused core is a pair of SMT4 cores. 103 */ 104 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 105 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 106 107 #define TYPE_PNV10_CHIP "pnv10-chip" 108 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 109 TYPE_PNV10_CHIP) 110 111 struct Pnv10Chip { 112 /*< private >*/ 113 PnvChip parent_obj; 114 115 /*< public >*/ 116 PnvADU adu; 117 PnvXive2 xive; 118 Pnv9Psi psi; 119 PnvLpcController lpc; 120 PnvChipTOD chiptod; 121 PnvOCC occ; 122 PnvSBE sbe; 123 PnvHomer homer; 124 PnvN1Chiplet n1_chiplet; 125 126 uint32_t nr_quads; 127 PnvQuad *quads; 128 129 #define PNV10_CHIP_MAX_PEC 2 130 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 131 132 #define PNV10_CHIP_MAX_I2C 4 133 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 134 }; 135 136 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 137 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 138 139 struct PnvChipClass { 140 /*< private >*/ 141 SysBusDeviceClass parent_class; 142 143 /*< public >*/ 144 uint64_t chip_cfam_id; 145 uint64_t cores_mask; 146 uint32_t num_pecs; 147 uint32_t num_phbs; 148 149 uint32_t i2c_num_engines; 150 const int *i2c_ports_per_engine; 151 152 DeviceRealize parent_realize; 153 154 /* Get PIR and TIR values for a CPU thread identified by core/thread id */ 155 void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id, 156 uint32_t *pir, uint32_t *tir); 157 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 158 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 159 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 160 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf); 161 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 162 void (*dt_populate)(PnvChip *chip, void *fdt); 163 void (*pic_print_info)(PnvChip *chip, GString *buf); 164 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 165 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 166 }; 167 168 #endif 169