1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_chiptod.h" 6 #include "hw/ppc/pnv_core.h" 7 #include "hw/ppc/pnv_homer.h" 8 #include "hw/ppc/pnv_n1_chiplet.h" 9 #include "hw/ppc/pnv_lpc.h" 10 #include "hw/ppc/pnv_occ.h" 11 #include "hw/ppc/pnv_psi.h" 12 #include "hw/ppc/pnv_sbe.h" 13 #include "hw/ppc/pnv_xive.h" 14 #include "hw/ppc/pnv_i2c.h" 15 #include "hw/sysbus.h" 16 17 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 18 PNV_CHIP) 19 20 struct PnvChip { 21 /*< private >*/ 22 SysBusDevice parent_obj; 23 24 /*< public >*/ 25 uint32_t chip_id; 26 uint64_t ram_start; 27 uint64_t ram_size; 28 29 uint32_t nr_cores; 30 uint32_t nr_threads; 31 uint64_t cores_mask; 32 PnvCore **cores; 33 34 uint32_t num_pecs; 35 36 MemoryRegion xscom_mmio; 37 MemoryRegion xscom; 38 AddressSpace xscom_as; 39 40 MemoryRegion *fw_mr; 41 gchar *dt_isa_nodename; 42 }; 43 44 #define TYPE_PNV8_CHIP "pnv8-chip" 45 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 46 TYPE_PNV8_CHIP) 47 48 struct Pnv8Chip { 49 /*< private >*/ 50 PnvChip parent_obj; 51 52 /*< public >*/ 53 MemoryRegion icp_mmio; 54 55 PnvLpcController lpc; 56 Pnv8Psi psi; 57 PnvOCC occ; 58 PnvHomer homer; 59 60 #define PNV8_CHIP_PHB3_MAX 4 61 /* 62 * The array is used to allow quick access to the phbs by 63 * pnv_ics_get_child() and pnv_ics_resend_child(). 64 */ 65 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 66 uint32_t num_phbs; 67 68 XICSFabric *xics; 69 }; 70 71 #define TYPE_PNV9_CHIP "pnv9-chip" 72 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 73 TYPE_PNV9_CHIP) 74 75 struct Pnv9Chip { 76 /*< private >*/ 77 PnvChip parent_obj; 78 79 /*< public >*/ 80 PnvXive xive; 81 Pnv9Psi psi; 82 PnvLpcController lpc; 83 PnvChipTOD chiptod; 84 PnvOCC occ; 85 PnvSBE sbe; 86 PnvHomer homer; 87 88 uint32_t nr_quads; 89 PnvQuad *quads; 90 91 #define PNV9_CHIP_MAX_PEC 3 92 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 93 94 #define PNV9_CHIP_MAX_I2C 4 95 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 96 }; 97 98 /* 99 * A SMT8 fused core is a pair of SMT4 cores. 100 */ 101 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 102 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 103 104 #define TYPE_PNV10_CHIP "pnv10-chip" 105 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 106 TYPE_PNV10_CHIP) 107 108 struct Pnv10Chip { 109 /*< private >*/ 110 PnvChip parent_obj; 111 112 /*< public >*/ 113 PnvXive2 xive; 114 Pnv9Psi psi; 115 PnvLpcController lpc; 116 PnvChipTOD chiptod; 117 PnvOCC occ; 118 PnvSBE sbe; 119 PnvHomer homer; 120 PnvN1Chiplet n1_chiplet; 121 122 uint32_t nr_quads; 123 PnvQuad *quads; 124 125 #define PNV10_CHIP_MAX_PEC 2 126 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 127 128 #define PNV10_CHIP_MAX_I2C 4 129 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 130 }; 131 132 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 133 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 134 135 struct PnvChipClass { 136 /*< private >*/ 137 SysBusDeviceClass parent_class; 138 139 /*< public >*/ 140 uint64_t chip_cfam_id; 141 uint64_t cores_mask; 142 uint32_t num_pecs; 143 uint32_t num_phbs; 144 145 uint32_t i2c_num_engines; 146 const int *i2c_ports_per_engine; 147 148 DeviceRealize parent_realize; 149 150 uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id); 151 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 152 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 153 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 154 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 155 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 156 void (*dt_populate)(PnvChip *chip, void *fdt); 157 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 158 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 159 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 160 }; 161 162 #endif 163