1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_adu.h" 6 #include "hw/ppc/pnv_chiptod.h" 7 #include "hw/ppc/pnv_core.h" 8 #include "hw/ppc/pnv_homer.h" 9 #include "hw/ppc/pnv_n1_chiplet.h" 10 #include "hw/ppc/pnv_lpc.h" 11 #include "hw/ppc/pnv_occ.h" 12 #include "hw/ppc/pnv_psi.h" 13 #include "hw/ppc/pnv_sbe.h" 14 #include "hw/ppc/pnv_xive.h" 15 #include "hw/ppc/pnv_i2c.h" 16 #include "hw/sysbus.h" 17 18 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 19 PNV_CHIP) 20 21 struct PnvChip { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 uint32_t chip_id; 27 uint64_t ram_start; 28 uint64_t ram_size; 29 30 bool big_core; 31 bool lpar_per_core; 32 uint32_t nr_cores; 33 uint32_t nr_threads; 34 uint64_t cores_mask; 35 PnvCore **cores; 36 37 uint32_t num_pecs; 38 39 MemoryRegion xscom_mmio; 40 MemoryRegion xscom; 41 AddressSpace xscom_as; 42 43 MemoryRegion *fw_mr; 44 gchar *dt_isa_nodename; 45 }; 46 47 #define TYPE_PNV8_CHIP "pnv8-chip" 48 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 49 TYPE_PNV8_CHIP) 50 51 struct Pnv8Chip { 52 /*< private >*/ 53 PnvChip parent_obj; 54 55 /*< public >*/ 56 MemoryRegion icp_mmio; 57 58 PnvLpcController lpc; 59 Pnv8Psi psi; 60 PnvOCC occ; 61 PnvHomer homer; 62 63 #define PNV8_CHIP_PHB3_MAX 4 64 /* 65 * The array is used to allow quick access to the phbs by 66 * pnv_ics_get_child() and pnv_ics_resend_child(). 67 */ 68 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 69 uint32_t num_phbs; 70 71 XICSFabric *xics; 72 }; 73 74 #define TYPE_PNV9_CHIP "pnv9-chip" 75 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 76 TYPE_PNV9_CHIP) 77 78 struct Pnv9Chip { 79 /*< private >*/ 80 PnvChip parent_obj; 81 82 /*< public >*/ 83 PnvADU adu; 84 PnvXive xive; 85 Pnv9Psi psi; 86 PnvLpcController lpc; 87 PnvChipTOD chiptod; 88 PnvOCC occ; 89 PnvSBE sbe; 90 PnvHomer homer; 91 92 uint32_t nr_quads; 93 PnvQuad *quads; 94 95 #define PNV9_CHIP_MAX_PEC 3 96 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 97 98 #define PNV9_CHIP_MAX_I2C 4 99 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 100 }; 101 102 /* 103 * A SMT8 fused core is a pair of SMT4 cores. 104 */ 105 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 106 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 107 108 #define TYPE_PNV10_CHIP "pnv10-chip" 109 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 110 TYPE_PNV10_CHIP) 111 112 struct Pnv10Chip { 113 /*< private >*/ 114 PnvChip parent_obj; 115 116 /*< public >*/ 117 PnvADU adu; 118 PnvXive2 xive; 119 Pnv9Psi psi; 120 PnvLpcController lpc; 121 PnvChipTOD chiptod; 122 PnvOCC occ; 123 PnvSBE sbe; 124 PnvHomer homer; 125 PnvN1Chiplet n1_chiplet; 126 127 uint32_t nr_quads; 128 PnvQuad *quads; 129 130 #define PNV10_CHIP_MAX_PEC 2 131 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 132 133 #define PNV10_CHIP_MAX_I2C 4 134 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 135 }; 136 137 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 138 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 139 140 struct PnvChipClass { 141 /*< private >*/ 142 SysBusDeviceClass parent_class; 143 144 /*< public >*/ 145 uint64_t chip_cfam_id; 146 uint64_t cores_mask; 147 uint32_t num_pecs; 148 uint32_t num_phbs; 149 150 uint32_t i2c_num_engines; 151 const int *i2c_ports_per_engine; 152 153 DeviceRealize parent_realize; 154 155 /* Get PIR and TIR values for a CPU thread identified by core/thread id */ 156 void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id, 157 uint32_t *pir, uint32_t *tir); 158 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 159 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 160 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 161 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf); 162 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 163 void (*dt_populate)(PnvChip *chip, void *fdt); 164 void (*pic_print_info)(PnvChip *chip, GString *buf); 165 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 166 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 167 }; 168 169 #endif 170