1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef enum PnvChipType { 42 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 43 PNV_CHIP_POWER8, /* AKA Venice */ 44 PNV_CHIP_POWER8NVL, /* AKA Naples */ 45 PNV_CHIP_POWER9, /* AKA Nimbus */ 46 } PnvChipType; 47 48 typedef struct PnvChip { 49 /*< private >*/ 50 SysBusDevice parent_obj; 51 52 /*< public >*/ 53 uint32_t chip_id; 54 uint64_t ram_start; 55 uint64_t ram_size; 56 57 uint32_t nr_cores; 58 uint64_t cores_mask; 59 PnvCore **cores; 60 61 MemoryRegion xscom_mmio; 62 MemoryRegion xscom; 63 AddressSpace xscom_as; 64 65 gchar *dt_isa_nodename; 66 } PnvChip; 67 68 #define TYPE_PNV8_CHIP "pnv8-chip" 69 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 70 71 typedef struct Pnv8Chip { 72 /*< private >*/ 73 PnvChip parent_obj; 74 75 /*< public >*/ 76 MemoryRegion icp_mmio; 77 78 PnvLpcController lpc; 79 Pnv8Psi psi; 80 PnvOCC occ; 81 PnvHomer homer; 82 } Pnv8Chip; 83 84 #define TYPE_PNV9_CHIP "pnv9-chip" 85 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 86 87 typedef struct Pnv9Chip { 88 /*< private >*/ 89 PnvChip parent_obj; 90 91 /*< public >*/ 92 PnvXive xive; 93 Pnv9Psi psi; 94 PnvLpcController lpc; 95 PnvOCC occ; 96 PnvHomer homer; 97 98 uint32_t nr_quads; 99 PnvQuad *quads; 100 } Pnv9Chip; 101 102 typedef struct PnvChipClass { 103 /*< private >*/ 104 SysBusDeviceClass parent_class; 105 106 /*< public >*/ 107 PnvChipType chip_type; 108 uint64_t chip_cfam_id; 109 uint64_t cores_mask; 110 111 DeviceRealize parent_realize; 112 113 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 114 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 115 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 116 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 117 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 118 void (*dt_populate)(PnvChip *chip, void *fdt); 119 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 120 } PnvChipClass; 121 122 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 123 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 124 125 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 126 #define PNV_CHIP_POWER8E(obj) \ 127 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 128 129 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 130 #define PNV_CHIP_POWER8(obj) \ 131 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 132 133 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 134 #define PNV_CHIP_POWER8NVL(obj) \ 135 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 136 137 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 138 #define PNV_CHIP_POWER9(obj) \ 139 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 140 141 /* 142 * This generates a HW chip id depending on an index, as found on a 143 * two socket system with dual chip modules : 144 * 145 * 0x0, 0x1, 0x10, 0x11 146 * 147 * 4 chips should be the maximum 148 * 149 * TODO: use a machine property to define the chip ids 150 */ 151 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 152 153 /* 154 * Converts back a HW chip id to an index. This is useful to calculate 155 * the MMIO addresses of some controllers which depend on the chip id. 156 */ 157 #define PNV_CHIP_INDEX(chip) \ 158 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 159 160 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 161 #define PNV_MACHINE(obj) \ 162 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 163 164 typedef struct PnvMachineState { 165 /*< private >*/ 166 MachineState parent_obj; 167 168 uint32_t initrd_base; 169 long initrd_size; 170 171 uint32_t num_chips; 172 PnvChip **chips; 173 174 ISABus *isa_bus; 175 uint32_t cpld_irqstate; 176 177 IPMIBmc *bmc; 178 Notifier powerdown_notifier; 179 180 PnvPnor *pnor; 181 } PnvMachineState; 182 183 static inline bool pnv_chip_is_power9(const PnvChip *chip) 184 { 185 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; 186 } 187 188 static inline bool pnv_is_power9(PnvMachineState *pnv) 189 { 190 return pnv_chip_is_power9(pnv->chips[0]); 191 } 192 193 #define PNV_FDT_ADDR 0x01000000 194 #define PNV_TIMEBASE_FREQ 512000000ULL 195 196 /* 197 * BMC helpers 198 */ 199 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 200 void pnv_bmc_powerdown(IPMIBmc *bmc); 201 IPMIBmc *pnv_bmc_create(void); 202 203 /* 204 * POWER8 MMIO base addresses 205 */ 206 #define PNV_XSCOM_SIZE 0x800000000ull 207 #define PNV_XSCOM_BASE(chip) \ 208 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 209 210 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 211 #define PNV_OCC_COMMON_AREA(chip) \ 212 (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 213 PNV_OCC_COMMON_AREA_SIZE)) 214 215 #define PNV_HOMER_SIZE 0x0000000000300000ull 216 #define PNV_HOMER_BASE(chip) \ 217 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 218 219 220 /* 221 * XSCOM 0x20109CA defines the ICP BAR: 222 * 223 * 0:29 : bits 14 to 43 of address to define 1 MB region. 224 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 225 * 31:63 : Constant 0 226 * 227 * Usually defined as : 228 * 229 * 0xffffe00200000000 -> 0x0003ffff80000000 230 * 0xffffe00600000000 -> 0x0003ffff80100000 231 * 0xffffe02200000000 -> 0x0003ffff80800000 232 * 0xffffe02600000000 -> 0x0003ffff80900000 233 */ 234 #define PNV_ICP_SIZE 0x0000000000100000ull 235 #define PNV_ICP_BASE(chip) \ 236 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 237 238 239 #define PNV_PSIHB_SIZE 0x0000000000100000ull 240 #define PNV_PSIHB_BASE(chip) \ 241 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 242 243 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 244 #define PNV_PSIHB_FSP_BASE(chip) \ 245 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 246 PNV_PSIHB_FSP_SIZE) 247 248 /* 249 * POWER9 MMIO base addresses 250 */ 251 #define PNV9_CHIP_BASE(chip, base) \ 252 ((base) + ((uint64_t) (chip)->chip_id << 42)) 253 254 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 255 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 256 257 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 258 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 259 260 #define PNV9_LPCM_SIZE 0x0000000100000000ull 261 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 262 263 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 264 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 265 266 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 267 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 268 269 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 270 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 271 272 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 273 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 274 275 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 276 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 277 278 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 279 #define PNV9_OCC_COMMON_AREA(chip) \ 280 (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 281 PNV9_OCC_COMMON_AREA_SIZE)) 282 283 #define PNV9_HOMER_SIZE 0x0000000000300000ull 284 #define PNV9_HOMER_BASE(chip) \ 285 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 286 #endif /* PPC_PNV_H */ 287