1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_psi.h" 28 #include "hw/ppc/pnv_occ.h" 29 #include "hw/ppc/pnv_xive.h" 30 #include "hw/ppc/pnv_core.h" 31 32 #define TYPE_PNV_CHIP "pnv-chip" 33 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 34 #define PNV_CHIP_CLASS(klass) \ 35 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 36 #define PNV_CHIP_GET_CLASS(obj) \ 37 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 38 39 typedef enum PnvChipType { 40 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 41 PNV_CHIP_POWER8, /* AKA Venice */ 42 PNV_CHIP_POWER8NVL, /* AKA Naples */ 43 PNV_CHIP_POWER9, /* AKA Nimbus */ 44 } PnvChipType; 45 46 typedef struct PnvChip { 47 /*< private >*/ 48 SysBusDevice parent_obj; 49 50 /*< public >*/ 51 uint32_t chip_id; 52 uint64_t ram_start; 53 uint64_t ram_size; 54 55 uint32_t nr_cores; 56 uint64_t cores_mask; 57 void *cores; 58 59 MemoryRegion xscom_mmio; 60 MemoryRegion xscom; 61 AddressSpace xscom_as; 62 63 gchar *dt_isa_nodename; 64 } PnvChip; 65 66 #define TYPE_PNV8_CHIP "pnv8-chip" 67 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 68 69 typedef struct Pnv8Chip { 70 /*< private >*/ 71 PnvChip parent_obj; 72 73 /*< public >*/ 74 MemoryRegion icp_mmio; 75 76 PnvLpcController lpc; 77 Pnv8Psi psi; 78 PnvOCC occ; 79 } Pnv8Chip; 80 81 #define TYPE_PNV9_CHIP "pnv9-chip" 82 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 83 84 typedef struct Pnv9Chip { 85 /*< private >*/ 86 PnvChip parent_obj; 87 88 /*< public >*/ 89 PnvXive xive; 90 Pnv9Psi psi; 91 PnvLpcController lpc; 92 PnvOCC occ; 93 94 uint32_t nr_quads; 95 PnvQuad *quads; 96 } Pnv9Chip; 97 98 typedef struct PnvChipClass { 99 /*< private >*/ 100 SysBusDeviceClass parent_class; 101 102 /*< public >*/ 103 PnvChipType chip_type; 104 uint64_t chip_cfam_id; 105 uint64_t cores_mask; 106 107 DeviceRealize parent_realize; 108 109 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 110 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 111 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 112 void (*dt_populate)(PnvChip *chip, void *fdt); 113 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 114 } PnvChipClass; 115 116 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 117 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 118 119 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 120 #define PNV_CHIP_POWER8E(obj) \ 121 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 122 123 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 124 #define PNV_CHIP_POWER8(obj) \ 125 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 126 127 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 128 #define PNV_CHIP_POWER8NVL(obj) \ 129 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 130 131 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 132 #define PNV_CHIP_POWER9(obj) \ 133 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 134 135 /* 136 * This generates a HW chip id depending on an index, as found on a 137 * two socket system with dual chip modules : 138 * 139 * 0x0, 0x1, 0x10, 0x11 140 * 141 * 4 chips should be the maximum 142 * 143 * TODO: use a machine property to define the chip ids 144 */ 145 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 146 147 /* 148 * Converts back a HW chip id to an index. This is useful to calculate 149 * the MMIO addresses of some controllers which depend on the chip id. 150 */ 151 #define PNV_CHIP_INDEX(chip) \ 152 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 153 154 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 155 #define PNV_MACHINE(obj) \ 156 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 157 158 typedef struct PnvMachineState { 159 /*< private >*/ 160 MachineState parent_obj; 161 162 uint32_t initrd_base; 163 long initrd_size; 164 165 uint32_t num_chips; 166 PnvChip **chips; 167 168 ISABus *isa_bus; 169 uint32_t cpld_irqstate; 170 171 IPMIBmc *bmc; 172 Notifier powerdown_notifier; 173 } PnvMachineState; 174 175 static inline bool pnv_chip_is_power9(const PnvChip *chip) 176 { 177 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; 178 } 179 180 static inline bool pnv_is_power9(PnvMachineState *pnv) 181 { 182 return pnv_chip_is_power9(pnv->chips[0]); 183 } 184 185 #define PNV_FDT_ADDR 0x01000000 186 #define PNV_TIMEBASE_FREQ 512000000ULL 187 188 /* 189 * BMC helpers 190 */ 191 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 192 void pnv_bmc_powerdown(IPMIBmc *bmc); 193 194 /* 195 * POWER8 MMIO base addresses 196 */ 197 #define PNV_XSCOM_SIZE 0x800000000ull 198 #define PNV_XSCOM_BASE(chip) \ 199 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 200 201 /* 202 * XSCOM 0x20109CA defines the ICP BAR: 203 * 204 * 0:29 : bits 14 to 43 of address to define 1 MB region. 205 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 206 * 31:63 : Constant 0 207 * 208 * Usually defined as : 209 * 210 * 0xffffe00200000000 -> 0x0003ffff80000000 211 * 0xffffe00600000000 -> 0x0003ffff80100000 212 * 0xffffe02200000000 -> 0x0003ffff80800000 213 * 0xffffe02600000000 -> 0x0003ffff80900000 214 */ 215 #define PNV_ICP_SIZE 0x0000000000100000ull 216 #define PNV_ICP_BASE(chip) \ 217 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 218 219 220 #define PNV_PSIHB_SIZE 0x0000000000100000ull 221 #define PNV_PSIHB_BASE(chip) \ 222 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 223 224 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 225 #define PNV_PSIHB_FSP_BASE(chip) \ 226 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 227 PNV_PSIHB_FSP_SIZE) 228 229 /* 230 * POWER9 MMIO base addresses 231 */ 232 #define PNV9_CHIP_BASE(chip, base) \ 233 ((base) + ((uint64_t) (chip)->chip_id << 42)) 234 235 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 236 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 237 238 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 239 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 240 241 #define PNV9_LPCM_SIZE 0x0000000100000000ull 242 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 243 244 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 245 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 246 247 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 248 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 249 250 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 251 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 252 253 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 254 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 255 256 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 257 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 258 259 #endif /* PPC_PNV_H */ 260