1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef struct PnvChip { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 uint32_t chip_id; 47 uint64_t ram_start; 48 uint64_t ram_size; 49 50 uint32_t nr_cores; 51 uint64_t cores_mask; 52 PnvCore **cores; 53 54 MemoryRegion xscom_mmio; 55 MemoryRegion xscom; 56 AddressSpace xscom_as; 57 58 gchar *dt_isa_nodename; 59 } PnvChip; 60 61 #define TYPE_PNV8_CHIP "pnv8-chip" 62 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 63 64 typedef struct Pnv8Chip { 65 /*< private >*/ 66 PnvChip parent_obj; 67 68 /*< public >*/ 69 MemoryRegion icp_mmio; 70 71 PnvLpcController lpc; 72 Pnv8Psi psi; 73 PnvOCC occ; 74 PnvHomer homer; 75 } Pnv8Chip; 76 77 #define TYPE_PNV9_CHIP "pnv9-chip" 78 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 79 80 typedef struct Pnv9Chip { 81 /*< private >*/ 82 PnvChip parent_obj; 83 84 /*< public >*/ 85 PnvXive xive; 86 Pnv9Psi psi; 87 PnvLpcController lpc; 88 PnvOCC occ; 89 PnvHomer homer; 90 91 uint32_t nr_quads; 92 PnvQuad *quads; 93 } Pnv9Chip; 94 95 /* 96 * A SMT8 fused core is a pair of SMT4 cores. 97 */ 98 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 99 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 100 101 #define TYPE_PNV10_CHIP "pnv10-chip" 102 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 103 104 typedef struct Pnv10Chip { 105 /*< private >*/ 106 PnvChip parent_obj; 107 108 /*< public >*/ 109 Pnv9Psi psi; 110 PnvLpcController lpc; 111 } Pnv10Chip; 112 113 typedef struct PnvChipClass { 114 /*< private >*/ 115 SysBusDeviceClass parent_class; 116 117 /*< public >*/ 118 uint64_t chip_cfam_id; 119 uint64_t cores_mask; 120 121 DeviceRealize parent_realize; 122 123 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 124 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 125 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 126 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 127 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 128 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 129 void (*dt_populate)(PnvChip *chip, void *fdt); 130 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 131 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 132 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 133 } PnvChipClass; 134 135 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 136 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 137 138 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 139 #define PNV_CHIP_POWER8E(obj) \ 140 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 141 142 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 143 #define PNV_CHIP_POWER8(obj) \ 144 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 145 146 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 147 #define PNV_CHIP_POWER8NVL(obj) \ 148 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 149 150 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 151 #define PNV_CHIP_POWER9(obj) \ 152 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 153 154 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 155 #define PNV_CHIP_POWER10(obj) \ 156 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 157 158 /* 159 * This generates a HW chip id depending on an index, as found on a 160 * two socket system with dual chip modules : 161 * 162 * 0x0, 0x1, 0x10, 0x11 163 * 164 * 4 chips should be the maximum 165 * 166 * TODO: use a machine property to define the chip ids 167 */ 168 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 169 170 /* 171 * Converts back a HW chip id to an index. This is useful to calculate 172 * the MMIO addresses of some controllers which depend on the chip id. 173 */ 174 #define PNV_CHIP_INDEX(chip) \ 175 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 176 177 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 178 179 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 180 #define PNV_MACHINE(obj) \ 181 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 182 #define PNV_MACHINE_GET_CLASS(obj) \ 183 OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) 184 #define PNV_MACHINE_CLASS(klass) \ 185 OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) 186 187 typedef struct PnvMachineState PnvMachineState; 188 189 typedef struct PnvMachineClass { 190 /*< private >*/ 191 MachineClass parent_class; 192 193 /*< public >*/ 194 const char *compat; 195 int compat_size; 196 197 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 198 } PnvMachineClass; 199 200 struct PnvMachineState { 201 /*< private >*/ 202 MachineState parent_obj; 203 204 uint32_t initrd_base; 205 long initrd_size; 206 207 uint32_t num_chips; 208 PnvChip **chips; 209 210 ISABus *isa_bus; 211 uint32_t cpld_irqstate; 212 213 IPMIBmc *bmc; 214 Notifier powerdown_notifier; 215 216 PnvPnor *pnor; 217 }; 218 219 PnvChip *pnv_get_chip(uint32_t chip_id); 220 221 #define PNV_FDT_ADDR 0x01000000 222 #define PNV_TIMEBASE_FREQ 512000000ULL 223 224 /* 225 * BMC helpers 226 */ 227 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 228 void pnv_bmc_powerdown(IPMIBmc *bmc); 229 IPMIBmc *pnv_bmc_create(void); 230 231 /* 232 * POWER8 MMIO base addresses 233 */ 234 #define PNV_XSCOM_SIZE 0x800000000ull 235 #define PNV_XSCOM_BASE(chip) \ 236 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 237 238 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 239 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 240 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 241 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 242 243 #define PNV_HOMER_SIZE 0x0000000000400000ull 244 #define PNV_HOMER_BASE(chip) \ 245 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 246 247 248 /* 249 * XSCOM 0x20109CA defines the ICP BAR: 250 * 251 * 0:29 : bits 14 to 43 of address to define 1 MB region. 252 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 253 * 31:63 : Constant 0 254 * 255 * Usually defined as : 256 * 257 * 0xffffe00200000000 -> 0x0003ffff80000000 258 * 0xffffe00600000000 -> 0x0003ffff80100000 259 * 0xffffe02200000000 -> 0x0003ffff80800000 260 * 0xffffe02600000000 -> 0x0003ffff80900000 261 */ 262 #define PNV_ICP_SIZE 0x0000000000100000ull 263 #define PNV_ICP_BASE(chip) \ 264 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 265 266 267 #define PNV_PSIHB_SIZE 0x0000000000100000ull 268 #define PNV_PSIHB_BASE(chip) \ 269 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 270 271 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 272 #define PNV_PSIHB_FSP_BASE(chip) \ 273 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 274 PNV_PSIHB_FSP_SIZE) 275 276 /* 277 * POWER9 MMIO base addresses 278 */ 279 #define PNV9_CHIP_BASE(chip, base) \ 280 ((base) + ((uint64_t) (chip)->chip_id << 42)) 281 282 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 283 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 284 285 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 286 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 287 288 #define PNV9_LPCM_SIZE 0x0000000100000000ull 289 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 290 291 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 292 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 293 294 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 295 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 296 297 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 298 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 299 300 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 301 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 302 303 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 304 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 305 306 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 307 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 308 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 309 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 310 311 #define PNV9_HOMER_SIZE 0x0000000000400000ull 312 #define PNV9_HOMER_BASE(chip) \ 313 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 314 315 /* 316 * POWER10 MMIO base addresses - 16TB stride per chip 317 */ 318 #define PNV10_CHIP_BASE(chip, base) \ 319 ((base) + ((uint64_t) (chip)->chip_id << 44)) 320 321 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 322 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 323 324 #define PNV10_LPCM_SIZE 0x0000000100000000ull 325 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 326 327 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 328 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 329 330 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 331 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 332 333 #endif /* PPC_PNV_H */ 334