1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef _PPC_PNV_H 20 #define _PPC_PNV_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 #include "hw/ipmi/ipmi.h" 25 #include "hw/ppc/pnv_lpc.h" 26 #include "hw/ppc/pnv_psi.h" 27 #include "hw/ppc/pnv_occ.h" 28 29 #define TYPE_PNV_CHIP "powernv-chip" 30 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 31 #define PNV_CHIP_CLASS(klass) \ 32 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 33 #define PNV_CHIP_GET_CLASS(obj) \ 34 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 35 36 typedef enum PnvChipType { 37 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 38 PNV_CHIP_POWER8, /* AKA Venice */ 39 PNV_CHIP_POWER8NVL, /* AKA Naples */ 40 PNV_CHIP_POWER9, /* AKA Nimbus */ 41 } PnvChipType; 42 43 typedef struct PnvChip { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 uint32_t chip_id; 49 uint64_t ram_start; 50 uint64_t ram_size; 51 52 uint32_t nr_cores; 53 uint64_t cores_mask; 54 void *cores; 55 56 hwaddr xscom_base; 57 MemoryRegion xscom_mmio; 58 MemoryRegion xscom; 59 AddressSpace xscom_as; 60 MemoryRegion icp_mmio; 61 62 PnvLpcController lpc; 63 PnvPsi psi; 64 PnvOCC occ; 65 } PnvChip; 66 67 typedef struct PnvChipClass { 68 /*< private >*/ 69 SysBusDeviceClass parent_class; 70 71 /*< public >*/ 72 PnvChipType chip_type; 73 uint64_t chip_cfam_id; 74 uint64_t cores_mask; 75 76 hwaddr xscom_base; 77 hwaddr xscom_core_base; 78 79 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 80 } PnvChipClass; 81 82 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 83 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 84 85 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 86 #define PNV_CHIP_POWER8E(obj) \ 87 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 88 89 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 90 #define PNV_CHIP_POWER8(obj) \ 91 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 92 93 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 94 #define PNV_CHIP_POWER8NVL(obj) \ 95 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 96 97 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 98 #define PNV_CHIP_POWER9(obj) \ 99 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 100 101 /* 102 * This generates a HW chip id depending on an index, as found on a 103 * two socket system with dual chip modules : 104 * 105 * 0x0, 0x1, 0x10, 0x11 106 * 107 * 4 chips should be the maximum 108 * 109 * TODO: use a machine property to define the chip ids 110 */ 111 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 112 113 /* 114 * Converts back a HW chip id to an index. This is useful to calculate 115 * the MMIO addresses of some controllers which depend on the chip id. 116 */ 117 #define PNV_CHIP_INDEX(chip) \ 118 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 119 120 #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") 121 #define POWERNV_MACHINE(obj) \ 122 OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) 123 124 typedef struct PnvMachineState { 125 /*< private >*/ 126 MachineState parent_obj; 127 128 uint32_t initrd_base; 129 long initrd_size; 130 131 uint32_t num_chips; 132 PnvChip **chips; 133 134 ISABus *isa_bus; 135 uint32_t cpld_irqstate; 136 137 IPMIBmc *bmc; 138 Notifier powerdown_notifier; 139 } PnvMachineState; 140 141 #define PNV_FDT_ADDR 0x01000000 142 #define PNV_TIMEBASE_FREQ 512000000ULL 143 144 /* 145 * BMC helpers 146 */ 147 void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); 148 void pnv_bmc_powerdown(IPMIBmc *bmc); 149 150 /* 151 * POWER8 MMIO base addresses 152 */ 153 #define PNV_XSCOM_SIZE 0x800000000ull 154 #define PNV_XSCOM_BASE(chip) \ 155 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 156 157 /* 158 * XSCOM 0x20109CA defines the ICP BAR: 159 * 160 * 0:29 : bits 14 to 43 of address to define 1 MB region. 161 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 162 * 31:63 : Constant 0 163 * 164 * Usually defined as : 165 * 166 * 0xffffe00200000000 -> 0x0003ffff80000000 167 * 0xffffe00600000000 -> 0x0003ffff80100000 168 * 0xffffe02200000000 -> 0x0003ffff80800000 169 * 0xffffe02600000000 -> 0x0003ffff80900000 170 */ 171 #define PNV_ICP_SIZE 0x0000000000100000ull 172 #define PNV_ICP_BASE(chip) \ 173 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 174 175 176 #define PNV_PSIHB_SIZE 0x0000000000100000ull 177 #define PNV_PSIHB_BASE(chip) \ 178 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 179 180 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 181 #define PNV_PSIHB_FSP_BASE(chip) \ 182 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 183 PNV_PSIHB_FSP_SIZE) 184 185 #endif /* _PPC_PNV_H */ 186