1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/pci-host/pnv_phb3.h" 34 #include "hw/pci-host/pnv_phb4.h" 35 #include "qom/object.h" 36 37 #define TYPE_PNV_CHIP "pnv-chip" 38 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 39 PNV_CHIP) 40 41 struct PnvChip { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 uint32_t chip_id; 47 uint64_t ram_start; 48 uint64_t ram_size; 49 50 uint32_t nr_cores; 51 uint32_t nr_threads; 52 uint64_t cores_mask; 53 PnvCore **cores; 54 55 uint32_t num_phbs; 56 uint32_t num_pecs; 57 58 MemoryRegion xscom_mmio; 59 MemoryRegion xscom; 60 AddressSpace xscom_as; 61 62 MemoryRegion *fw_mr; 63 gchar *dt_isa_nodename; 64 }; 65 66 #define TYPE_PNV8_CHIP "pnv8-chip" 67 typedef struct Pnv8Chip Pnv8Chip; 68 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 69 TYPE_PNV8_CHIP) 70 71 struct Pnv8Chip { 72 /*< private >*/ 73 PnvChip parent_obj; 74 75 /*< public >*/ 76 MemoryRegion icp_mmio; 77 78 PnvLpcController lpc; 79 Pnv8Psi psi; 80 PnvOCC occ; 81 PnvHomer homer; 82 83 #define PNV8_CHIP_PHB3_MAX 4 84 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; 85 86 XICSFabric *xics; 87 }; 88 89 #define TYPE_PNV9_CHIP "pnv9-chip" 90 typedef struct Pnv9Chip Pnv9Chip; 91 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 92 TYPE_PNV9_CHIP) 93 94 struct Pnv9Chip { 95 /*< private >*/ 96 PnvChip parent_obj; 97 98 /*< public >*/ 99 PnvXive xive; 100 Pnv9Psi psi; 101 PnvLpcController lpc; 102 PnvOCC occ; 103 PnvHomer homer; 104 105 uint32_t nr_quads; 106 PnvQuad *quads; 107 108 #define PNV9_CHIP_MAX_PEC 3 109 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 110 }; 111 112 /* 113 * A SMT8 fused core is a pair of SMT4 cores. 114 */ 115 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 116 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 117 118 #define TYPE_PNV10_CHIP "pnv10-chip" 119 typedef struct Pnv10Chip Pnv10Chip; 120 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 121 TYPE_PNV10_CHIP) 122 123 struct Pnv10Chip { 124 /*< private >*/ 125 PnvChip parent_obj; 126 127 /*< public >*/ 128 Pnv9Psi psi; 129 PnvLpcController lpc; 130 }; 131 132 struct PnvChipClass { 133 /*< private >*/ 134 SysBusDeviceClass parent_class; 135 136 /*< public >*/ 137 uint64_t chip_cfam_id; 138 uint64_t cores_mask; 139 uint32_t num_phbs; 140 uint32_t num_pecs; 141 142 DeviceRealize parent_realize; 143 144 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 145 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 146 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 147 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 148 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 149 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 150 void (*dt_populate)(PnvChip *chip, void *fdt); 151 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 152 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 153 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 154 }; 155 156 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 157 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 158 159 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 160 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, 161 TYPE_PNV_CHIP_POWER8E) 162 163 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 164 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, 165 TYPE_PNV_CHIP_POWER8) 166 167 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 168 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, 169 TYPE_PNV_CHIP_POWER8NVL) 170 171 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 172 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, 173 TYPE_PNV_CHIP_POWER9) 174 175 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") 176 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, 177 TYPE_PNV_CHIP_POWER10) 178 179 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 180 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); 181 182 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 183 typedef struct PnvMachineClass PnvMachineClass; 184 typedef struct PnvMachineState PnvMachineState; 185 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, 186 PNV_MACHINE, TYPE_PNV_MACHINE) 187 188 189 struct PnvMachineClass { 190 /*< private >*/ 191 MachineClass parent_class; 192 193 /*< public >*/ 194 const char *compat; 195 int compat_size; 196 197 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 198 }; 199 200 struct PnvMachineState { 201 /*< private >*/ 202 MachineState parent_obj; 203 204 uint32_t initrd_base; 205 long initrd_size; 206 207 uint32_t num_chips; 208 PnvChip **chips; 209 210 ISABus *isa_bus; 211 uint32_t cpld_irqstate; 212 213 IPMIBmc *bmc; 214 Notifier powerdown_notifier; 215 216 PnvPnor *pnor; 217 218 hwaddr fw_load_addr; 219 }; 220 221 #define PNV_FDT_ADDR 0x01000000 222 #define PNV_TIMEBASE_FREQ 512000000ULL 223 224 /* 225 * BMC helpers 226 */ 227 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 228 void pnv_bmc_powerdown(IPMIBmc *bmc); 229 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 230 IPMIBmc *pnv_bmc_find(Error **errp); 231 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 232 233 /* 234 * POWER8 MMIO base addresses 235 */ 236 #define PNV_XSCOM_SIZE 0x800000000ull 237 #define PNV_XSCOM_BASE(chip) \ 238 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 239 240 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 241 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 242 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 243 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 244 245 #define PNV_HOMER_SIZE 0x0000000000400000ull 246 #define PNV_HOMER_BASE(chip) \ 247 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) 248 249 250 /* 251 * XSCOM 0x20109CA defines the ICP BAR: 252 * 253 * 0:29 : bits 14 to 43 of address to define 1 MB region. 254 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 255 * 31:63 : Constant 0 256 * 257 * Usually defined as : 258 * 259 * 0xffffe00200000000 -> 0x0003ffff80000000 260 * 0xffffe00600000000 -> 0x0003ffff80100000 261 * 0xffffe02200000000 -> 0x0003ffff80800000 262 * 0xffffe02600000000 -> 0x0003ffff80900000 263 */ 264 #define PNV_ICP_SIZE 0x0000000000100000ull 265 #define PNV_ICP_BASE(chip) \ 266 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) 267 268 269 #define PNV_PSIHB_SIZE 0x0000000000100000ull 270 #define PNV_PSIHB_BASE(chip) \ 271 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) 272 273 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 274 #define PNV_PSIHB_FSP_BASE(chip) \ 275 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ 276 PNV_PSIHB_FSP_SIZE) 277 278 /* 279 * POWER9 MMIO base addresses 280 */ 281 #define PNV9_CHIP_BASE(chip, base) \ 282 ((base) + ((uint64_t) (chip)->chip_id << 42)) 283 284 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 285 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 286 287 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 288 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 289 290 #define PNV9_LPCM_SIZE 0x0000000100000000ull 291 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 292 293 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 294 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 295 296 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 297 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 298 299 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 300 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 301 302 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 303 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 304 305 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 306 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 307 308 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 309 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 310 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 311 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 312 313 #define PNV9_HOMER_SIZE 0x0000000000400000ull 314 #define PNV9_HOMER_BASE(chip) \ 315 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) 316 317 /* 318 * POWER10 MMIO base addresses - 16TB stride per chip 319 */ 320 #define PNV10_CHIP_BASE(chip, base) \ 321 ((base) + ((uint64_t) (chip)->chip_id << 44)) 322 323 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 324 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 325 326 #define PNV10_LPCM_SIZE 0x0000000100000000ull 327 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 328 329 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 330 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 331 332 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 333 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 334 335 #endif /* PPC_PNV_H */ 336