1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/pci-host/pnv_phb3.h" 34 #include "hw/pci-host/pnv_phb4.h" 35 36 #define TYPE_PNV_CHIP "pnv-chip" 37 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 38 #define PNV_CHIP_CLASS(klass) \ 39 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 40 #define PNV_CHIP_GET_CLASS(obj) \ 41 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 42 43 typedef struct PnvChip { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 uint32_t chip_id; 49 uint64_t ram_start; 50 uint64_t ram_size; 51 52 uint32_t nr_cores; 53 uint32_t nr_threads; 54 uint64_t cores_mask; 55 PnvCore **cores; 56 57 uint32_t num_phbs; 58 59 MemoryRegion xscom_mmio; 60 MemoryRegion xscom; 61 AddressSpace xscom_as; 62 63 gchar *dt_isa_nodename; 64 } PnvChip; 65 66 #define TYPE_PNV8_CHIP "pnv8-chip" 67 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 68 69 typedef struct Pnv8Chip { 70 /*< private >*/ 71 PnvChip parent_obj; 72 73 /*< public >*/ 74 MemoryRegion icp_mmio; 75 76 PnvLpcController lpc; 77 Pnv8Psi psi; 78 PnvOCC occ; 79 PnvHomer homer; 80 81 #define PNV8_CHIP_PHB3_MAX 4 82 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; 83 84 XICSFabric *xics; 85 } Pnv8Chip; 86 87 #define TYPE_PNV9_CHIP "pnv9-chip" 88 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 89 90 typedef struct Pnv9Chip { 91 /*< private >*/ 92 PnvChip parent_obj; 93 94 /*< public >*/ 95 PnvXive xive; 96 Pnv9Psi psi; 97 PnvLpcController lpc; 98 PnvOCC occ; 99 PnvHomer homer; 100 101 uint32_t nr_quads; 102 PnvQuad *quads; 103 104 #define PNV9_CHIP_MAX_PEC 3 105 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 106 } Pnv9Chip; 107 108 /* 109 * A SMT8 fused core is a pair of SMT4 cores. 110 */ 111 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 112 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 113 114 #define TYPE_PNV10_CHIP "pnv10-chip" 115 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 116 117 typedef struct Pnv10Chip { 118 /*< private >*/ 119 PnvChip parent_obj; 120 121 /*< public >*/ 122 Pnv9Psi psi; 123 PnvLpcController lpc; 124 } Pnv10Chip; 125 126 typedef struct PnvChipClass { 127 /*< private >*/ 128 SysBusDeviceClass parent_class; 129 130 /*< public >*/ 131 uint64_t chip_cfam_id; 132 uint64_t cores_mask; 133 uint32_t num_phbs; 134 135 DeviceRealize parent_realize; 136 137 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 138 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 139 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 140 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 141 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 142 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 143 void (*dt_populate)(PnvChip *chip, void *fdt); 144 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 145 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 146 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 147 } PnvChipClass; 148 149 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 150 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 151 152 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 153 #define PNV_CHIP_POWER8E(obj) \ 154 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 155 156 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 157 #define PNV_CHIP_POWER8(obj) \ 158 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 159 160 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 161 #define PNV_CHIP_POWER8NVL(obj) \ 162 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 163 164 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 165 #define PNV_CHIP_POWER9(obj) \ 166 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 167 168 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 169 #define PNV_CHIP_POWER10(obj) \ 170 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 171 172 /* 173 * This generates a HW chip id depending on an index, as found on a 174 * two socket system with dual chip modules : 175 * 176 * 0x0, 0x1, 0x10, 0x11 177 * 178 * 4 chips should be the maximum 179 * 180 * TODO: use a machine property to define the chip ids 181 */ 182 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 183 184 /* 185 * Converts back a HW chip id to an index. This is useful to calculate 186 * the MMIO addresses of some controllers which depend on the chip id. 187 */ 188 #define PNV_CHIP_INDEX(chip) \ 189 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 190 191 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 192 193 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 194 #define PNV_MACHINE(obj) \ 195 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 196 #define PNV_MACHINE_GET_CLASS(obj) \ 197 OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) 198 #define PNV_MACHINE_CLASS(klass) \ 199 OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) 200 201 typedef struct PnvMachineState PnvMachineState; 202 203 typedef struct PnvMachineClass { 204 /*< private >*/ 205 MachineClass parent_class; 206 207 /*< public >*/ 208 const char *compat; 209 int compat_size; 210 211 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 212 } PnvMachineClass; 213 214 struct PnvMachineState { 215 /*< private >*/ 216 MachineState parent_obj; 217 218 uint32_t initrd_base; 219 long initrd_size; 220 221 uint32_t num_chips; 222 PnvChip **chips; 223 224 ISABus *isa_bus; 225 uint32_t cpld_irqstate; 226 227 IPMIBmc *bmc; 228 Notifier powerdown_notifier; 229 230 PnvPnor *pnor; 231 232 hwaddr fw_load_addr; 233 }; 234 235 #define PNV_FDT_ADDR 0x01000000 236 #define PNV_TIMEBASE_FREQ 512000000ULL 237 238 /* 239 * BMC helpers 240 */ 241 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 242 void pnv_bmc_powerdown(IPMIBmc *bmc); 243 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 244 245 /* 246 * POWER8 MMIO base addresses 247 */ 248 #define PNV_XSCOM_SIZE 0x800000000ull 249 #define PNV_XSCOM_BASE(chip) \ 250 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 251 252 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 253 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 254 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 255 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 256 257 #define PNV_HOMER_SIZE 0x0000000000400000ull 258 #define PNV_HOMER_BASE(chip) \ 259 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 260 261 262 /* 263 * XSCOM 0x20109CA defines the ICP BAR: 264 * 265 * 0:29 : bits 14 to 43 of address to define 1 MB region. 266 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 267 * 31:63 : Constant 0 268 * 269 * Usually defined as : 270 * 271 * 0xffffe00200000000 -> 0x0003ffff80000000 272 * 0xffffe00600000000 -> 0x0003ffff80100000 273 * 0xffffe02200000000 -> 0x0003ffff80800000 274 * 0xffffe02600000000 -> 0x0003ffff80900000 275 */ 276 #define PNV_ICP_SIZE 0x0000000000100000ull 277 #define PNV_ICP_BASE(chip) \ 278 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 279 280 281 #define PNV_PSIHB_SIZE 0x0000000000100000ull 282 #define PNV_PSIHB_BASE(chip) \ 283 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 284 285 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 286 #define PNV_PSIHB_FSP_BASE(chip) \ 287 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 288 PNV_PSIHB_FSP_SIZE) 289 290 /* 291 * POWER9 MMIO base addresses 292 */ 293 #define PNV9_CHIP_BASE(chip, base) \ 294 ((base) + ((uint64_t) (chip)->chip_id << 42)) 295 296 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 297 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 298 299 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 300 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 301 302 #define PNV9_LPCM_SIZE 0x0000000100000000ull 303 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 304 305 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 306 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 307 308 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 309 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 310 311 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 312 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 313 314 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 315 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 316 317 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 318 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 319 320 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 321 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 322 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 323 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 324 325 #define PNV9_HOMER_SIZE 0x0000000000400000ull 326 #define PNV9_HOMER_BASE(chip) \ 327 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 328 329 /* 330 * POWER10 MMIO base addresses - 16TB stride per chip 331 */ 332 #define PNV10_CHIP_BASE(chip, base) \ 333 ((base) + ((uint64_t) (chip)->chip_id << 44)) 334 335 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 336 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 337 338 #define PNV10_LPCM_SIZE 0x0000000100000000ull 339 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 340 341 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 342 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 343 344 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 345 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 346 347 #endif /* PPC_PNV_H */ 348