xref: /openbmc/qemu/include/hw/ppc/pnv.h (revision 70f168f8)
1 /*
2  * QEMU PowerPC PowerNV various definitions
3  *
4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef PPC_PNV_H
21 #define PPC_PNV_H
22 
23 #include "cpu.h"
24 #include "hw/boards.h"
25 #include "hw/sysbus.h"
26 #include "hw/ipmi/ipmi.h"
27 #include "hw/ppc/pnv_pnor.h"
28 
29 #define TYPE_PNV_CHIP "pnv-chip"
30 
31 typedef struct PnvChip PnvChip;
32 typedef struct Pnv8Chip Pnv8Chip;
33 typedef struct Pnv9Chip Pnv9Chip;
34 typedef struct Pnv10Chip Pnv10Chip;
35 
36 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
37 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
38 
39 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
40 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
41                          TYPE_PNV_CHIP_POWER8E)
42 
43 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
44 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
45                          TYPE_PNV_CHIP_POWER8)
46 
47 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
48 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
49                          TYPE_PNV_CHIP_POWER8NVL)
50 
51 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2")
52 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
53                          TYPE_PNV_CHIP_POWER9)
54 
55 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
56 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
57                          TYPE_PNV_CHIP_POWER10)
58 
59 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
60 
61 typedef struct PnvPHB PnvPHB;
62 
63 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
64 typedef struct PnvMachineClass PnvMachineClass;
65 typedef struct PnvMachineState PnvMachineState;
66 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
67                      PNV_MACHINE, TYPE_PNV_MACHINE)
68 
69 
70 struct PnvMachineClass {
71     /*< private >*/
72     MachineClass parent_class;
73 
74     /*< public >*/
75     const char *compat;
76     int compat_size;
77 
78     void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
79 };
80 
81 struct PnvMachineState {
82     /*< private >*/
83     MachineState parent_obj;
84 
85     uint32_t     initrd_base;
86     long         initrd_size;
87 
88     uint32_t     num_chips;
89     PnvChip      **chips;
90 
91     ISABus       *isa_bus;
92     uint32_t     cpld_irqstate;
93 
94     IPMIBmc      *bmc;
95     Notifier     powerdown_notifier;
96 
97     PnvPnor      *pnor;
98 
99     hwaddr       fw_load_addr;
100 };
101 
102 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
103 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
104 
105 #define PNV_FDT_ADDR          0x01000000
106 #define PNV_TIMEBASE_FREQ     512000000ULL
107 
108 /*
109  * BMC helpers
110  */
111 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
112 void pnv_bmc_powerdown(IPMIBmc *bmc);
113 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
114 IPMIBmc *pnv_bmc_find(Error **errp);
115 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
116 
117 /*
118  * POWER8 MMIO base addresses
119  */
120 #define PNV_XSCOM_SIZE        0x800000000ull
121 #define PNV_XSCOM_BASE(chip)                                            \
122     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
123 
124 #define PNV_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
125 #define PNV_OCC_COMMON_AREA_BASE    0x7fff800000ull
126 #define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \
127     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
128 
129 #define PNV_HOMER_SIZE              0x0000000000400000ull
130 #define PNV_HOMER_BASE(chip)                                            \
131     (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
132 
133 
134 /*
135  * XSCOM 0x20109CA defines the ICP BAR:
136  *
137  * 0:29   : bits 14 to 43 of address to define 1 MB region.
138  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
139  * 31:63  : Constant 0
140  *
141  * Usually defined as :
142  *
143  *      0xffffe00200000000 -> 0x0003ffff80000000
144  *      0xffffe00600000000 -> 0x0003ffff80100000
145  *      0xffffe02200000000 -> 0x0003ffff80800000
146  *      0xffffe02600000000 -> 0x0003ffff80900000
147  */
148 #define PNV_ICP_SIZE         0x0000000000100000ull
149 #define PNV_ICP_BASE(chip)                                              \
150     (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
151 
152 
153 #define PNV_PSIHB_SIZE       0x0000000000100000ull
154 #define PNV_PSIHB_BASE(chip) \
155     (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
156 
157 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
158 #define PNV_PSIHB_FSP_BASE(chip) \
159     (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
160      PNV_PSIHB_FSP_SIZE)
161 
162 /*
163  * POWER9 MMIO base addresses
164  */
165 #define PNV9_CHIP_BASE(chip, base)   \
166     ((base) + ((uint64_t) (chip)->chip_id << 42))
167 
168 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
169 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
170 
171 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
172 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
173 
174 #define PNV9_LPCM_SIZE               0x0000000100000000ull
175 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
176 
177 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
178 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
179 
180 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
181 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
182 
183 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
184 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
185 
186 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
187 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
188 
189 #define PNV9_XSCOM_SIZE              0x0000000400000000ull
190 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
191 
192 #define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
193 #define PNV9_OCC_COMMON_AREA_BASE    0x203fff800000ull
194 #define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \
195     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
196 
197 #define PNV9_HOMER_SIZE              0x0000000000400000ull
198 #define PNV9_HOMER_BASE(chip)                                           \
199     (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
200 
201 /*
202  * POWER10 MMIO base addresses - 16TB stride per chip
203  */
204 #define PNV10_CHIP_BASE(chip, base)   \
205     ((base) + ((uint64_t) (chip)->chip_id << 44))
206 
207 #define PNV10_XSCOM_SIZE             0x0000000400000000ull
208 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
209 
210 #define PNV10_LPCM_SIZE             0x0000000100000000ull
211 #define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
212 
213 #define PNV10_XIVE2_IC_SIZE         0x0000000002000000ull
214 #define PNV10_XIVE2_IC_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
215 
216 #define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
217 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
218 
219 #define PNV10_PSIHB_SIZE            0x0000000000100000ull
220 #define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
221 
222 #define PNV10_XIVE2_TM_SIZE         0x0000000000040000ull
223 #define PNV10_XIVE2_TM_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
224 
225 #define PNV10_XIVE2_NVC_SIZE        0x0000000008000000ull
226 #define PNV10_XIVE2_NVC_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
227 
228 #define PNV10_XIVE2_NVPG_SIZE       0x0000010000000000ull
229 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
230 
231 #define PNV10_XIVE2_ESB_SIZE        0x0000010000000000ull
232 #define PNV10_XIVE2_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
233 
234 #define PNV10_XIVE2_END_SIZE        0x0000020000000000ull
235 #define PNV10_XIVE2_END_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
236 
237 #define PNV10_OCC_COMMON_AREA_SIZE  0x0000000000800000ull
238 #define PNV10_OCC_COMMON_AREA_BASE  0x300fff800000ull
239 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE +       \
240     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
241 
242 #define PNV10_HOMER_SIZE              0x0000000000400000ull
243 #define PNV10_HOMER_BASE(chip)                                           \
244     (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
245 
246 #endif /* PPC_PNV_H */
247