1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef enum PnvChipType { 42 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 43 PNV_CHIP_POWER8, /* AKA Venice */ 44 PNV_CHIP_POWER8NVL, /* AKA Naples */ 45 PNV_CHIP_POWER9, /* AKA Nimbus */ 46 PNV_CHIP_POWER10, /* AKA TBD */ 47 } PnvChipType; 48 49 typedef struct PnvChip { 50 /*< private >*/ 51 SysBusDevice parent_obj; 52 53 /*< public >*/ 54 uint32_t chip_id; 55 uint64_t ram_start; 56 uint64_t ram_size; 57 58 uint32_t nr_cores; 59 uint64_t cores_mask; 60 PnvCore **cores; 61 62 MemoryRegion xscom_mmio; 63 MemoryRegion xscom; 64 AddressSpace xscom_as; 65 66 gchar *dt_isa_nodename; 67 } PnvChip; 68 69 #define TYPE_PNV8_CHIP "pnv8-chip" 70 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 71 72 typedef struct Pnv8Chip { 73 /*< private >*/ 74 PnvChip parent_obj; 75 76 /*< public >*/ 77 MemoryRegion icp_mmio; 78 79 PnvLpcController lpc; 80 Pnv8Psi psi; 81 PnvOCC occ; 82 PnvHomer homer; 83 } Pnv8Chip; 84 85 #define TYPE_PNV9_CHIP "pnv9-chip" 86 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 87 88 typedef struct Pnv9Chip { 89 /*< private >*/ 90 PnvChip parent_obj; 91 92 /*< public >*/ 93 PnvXive xive; 94 Pnv9Psi psi; 95 PnvLpcController lpc; 96 PnvOCC occ; 97 PnvHomer homer; 98 99 uint32_t nr_quads; 100 PnvQuad *quads; 101 } Pnv9Chip; 102 103 /* 104 * A SMT8 fused core is a pair of SMT4 cores. 105 */ 106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 107 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 108 109 #define TYPE_PNV10_CHIP "pnv10-chip" 110 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 111 112 typedef struct Pnv10Chip { 113 /*< private >*/ 114 PnvChip parent_obj; 115 } Pnv10Chip; 116 117 typedef struct PnvChipClass { 118 /*< private >*/ 119 SysBusDeviceClass parent_class; 120 121 /*< public >*/ 122 PnvChipType chip_type; 123 uint64_t chip_cfam_id; 124 uint64_t cores_mask; 125 126 DeviceRealize parent_realize; 127 128 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 129 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 130 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 131 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 132 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 133 void (*dt_populate)(PnvChip *chip, void *fdt); 134 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 135 } PnvChipClass; 136 137 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 138 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 139 140 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 141 #define PNV_CHIP_POWER8E(obj) \ 142 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 143 144 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 145 #define PNV_CHIP_POWER8(obj) \ 146 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 147 148 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 149 #define PNV_CHIP_POWER8NVL(obj) \ 150 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 151 152 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 153 #define PNV_CHIP_POWER9(obj) \ 154 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 155 156 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 157 #define PNV_CHIP_POWER10(obj) \ 158 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 159 160 /* 161 * This generates a HW chip id depending on an index, as found on a 162 * two socket system with dual chip modules : 163 * 164 * 0x0, 0x1, 0x10, 0x11 165 * 166 * 4 chips should be the maximum 167 * 168 * TODO: use a machine property to define the chip ids 169 */ 170 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 171 172 /* 173 * Converts back a HW chip id to an index. This is useful to calculate 174 * the MMIO addresses of some controllers which depend on the chip id. 175 */ 176 #define PNV_CHIP_INDEX(chip) \ 177 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 178 179 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 180 181 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 182 #define PNV_MACHINE(obj) \ 183 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 184 185 typedef struct PnvMachineState { 186 /*< private >*/ 187 MachineState parent_obj; 188 189 uint32_t initrd_base; 190 long initrd_size; 191 192 uint32_t num_chips; 193 PnvChip **chips; 194 195 ISABus *isa_bus; 196 uint32_t cpld_irqstate; 197 198 IPMIBmc *bmc; 199 Notifier powerdown_notifier; 200 201 PnvPnor *pnor; 202 } PnvMachineState; 203 204 static inline bool pnv_chip_is_power9(const PnvChip *chip) 205 { 206 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; 207 } 208 209 static inline bool pnv_is_power9(PnvMachineState *pnv) 210 { 211 return pnv_chip_is_power9(pnv->chips[0]); 212 } 213 214 PnvChip *pnv_get_chip(uint32_t chip_id); 215 216 #define PNV_FDT_ADDR 0x01000000 217 #define PNV_TIMEBASE_FREQ 512000000ULL 218 219 static inline bool pnv_chip_is_power10(const PnvChip *chip) 220 { 221 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10; 222 } 223 224 static inline bool pnv_is_power10(PnvMachineState *pnv) 225 { 226 return pnv_chip_is_power10(pnv->chips[0]); 227 } 228 229 /* 230 * BMC helpers 231 */ 232 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 233 void pnv_bmc_powerdown(IPMIBmc *bmc); 234 IPMIBmc *pnv_bmc_create(void); 235 236 /* 237 * POWER8 MMIO base addresses 238 */ 239 #define PNV_XSCOM_SIZE 0x800000000ull 240 #define PNV_XSCOM_BASE(chip) \ 241 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 242 243 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 244 #define PNV_OCC_COMMON_AREA(chip) \ 245 (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 246 PNV_OCC_COMMON_AREA_SIZE)) 247 248 #define PNV_HOMER_SIZE 0x0000000000300000ull 249 #define PNV_HOMER_BASE(chip) \ 250 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 251 252 253 /* 254 * XSCOM 0x20109CA defines the ICP BAR: 255 * 256 * 0:29 : bits 14 to 43 of address to define 1 MB region. 257 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 258 * 31:63 : Constant 0 259 * 260 * Usually defined as : 261 * 262 * 0xffffe00200000000 -> 0x0003ffff80000000 263 * 0xffffe00600000000 -> 0x0003ffff80100000 264 * 0xffffe02200000000 -> 0x0003ffff80800000 265 * 0xffffe02600000000 -> 0x0003ffff80900000 266 */ 267 #define PNV_ICP_SIZE 0x0000000000100000ull 268 #define PNV_ICP_BASE(chip) \ 269 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 270 271 272 #define PNV_PSIHB_SIZE 0x0000000000100000ull 273 #define PNV_PSIHB_BASE(chip) \ 274 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 275 276 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 277 #define PNV_PSIHB_FSP_BASE(chip) \ 278 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 279 PNV_PSIHB_FSP_SIZE) 280 281 /* 282 * POWER9 MMIO base addresses 283 */ 284 #define PNV9_CHIP_BASE(chip, base) \ 285 ((base) + ((uint64_t) (chip)->chip_id << 42)) 286 287 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 288 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 289 290 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 291 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 292 293 #define PNV9_LPCM_SIZE 0x0000000100000000ull 294 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 295 296 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 297 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 298 299 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 300 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 301 302 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 303 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 304 305 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 306 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 307 308 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 309 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 310 311 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 312 #define PNV9_OCC_COMMON_AREA(chip) \ 313 (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 314 PNV9_OCC_COMMON_AREA_SIZE)) 315 316 #define PNV9_HOMER_SIZE 0x0000000000300000ull 317 #define PNV9_HOMER_BASE(chip) \ 318 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 319 320 /* 321 * POWER10 MMIO base addresses - 16TB stride per chip 322 */ 323 #define PNV10_CHIP_BASE(chip, base) \ 324 ((base) + ((uint64_t) (chip)->chip_id << 44)) 325 326 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 327 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 328 329 #endif /* PPC_PNV_H */ 330