1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef struct PnvChip { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 uint32_t chip_id; 47 uint64_t ram_start; 48 uint64_t ram_size; 49 50 uint32_t nr_cores; 51 uint64_t cores_mask; 52 PnvCore **cores; 53 54 MemoryRegion xscom_mmio; 55 MemoryRegion xscom; 56 AddressSpace xscom_as; 57 58 gchar *dt_isa_nodename; 59 } PnvChip; 60 61 #define TYPE_PNV8_CHIP "pnv8-chip" 62 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 63 64 typedef struct Pnv8Chip { 65 /*< private >*/ 66 PnvChip parent_obj; 67 68 /*< public >*/ 69 MemoryRegion icp_mmio; 70 71 PnvLpcController lpc; 72 Pnv8Psi psi; 73 PnvOCC occ; 74 PnvHomer homer; 75 76 XICSFabric *xics; 77 } Pnv8Chip; 78 79 #define TYPE_PNV9_CHIP "pnv9-chip" 80 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 81 82 typedef struct Pnv9Chip { 83 /*< private >*/ 84 PnvChip parent_obj; 85 86 /*< public >*/ 87 PnvXive xive; 88 Pnv9Psi psi; 89 PnvLpcController lpc; 90 PnvOCC occ; 91 PnvHomer homer; 92 93 uint32_t nr_quads; 94 PnvQuad *quads; 95 } Pnv9Chip; 96 97 /* 98 * A SMT8 fused core is a pair of SMT4 cores. 99 */ 100 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 101 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 102 103 #define TYPE_PNV10_CHIP "pnv10-chip" 104 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 105 106 typedef struct Pnv10Chip { 107 /*< private >*/ 108 PnvChip parent_obj; 109 110 /*< public >*/ 111 Pnv9Psi psi; 112 PnvLpcController lpc; 113 } Pnv10Chip; 114 115 typedef struct PnvChipClass { 116 /*< private >*/ 117 SysBusDeviceClass parent_class; 118 119 /*< public >*/ 120 uint64_t chip_cfam_id; 121 uint64_t cores_mask; 122 123 DeviceRealize parent_realize; 124 125 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 126 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 127 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 128 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 129 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 130 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 131 void (*dt_populate)(PnvChip *chip, void *fdt); 132 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 133 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 134 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 135 } PnvChipClass; 136 137 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 138 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 139 140 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 141 #define PNV_CHIP_POWER8E(obj) \ 142 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 143 144 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 145 #define PNV_CHIP_POWER8(obj) \ 146 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 147 148 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 149 #define PNV_CHIP_POWER8NVL(obj) \ 150 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 151 152 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 153 #define PNV_CHIP_POWER9(obj) \ 154 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 155 156 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 157 #define PNV_CHIP_POWER10(obj) \ 158 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 159 160 /* 161 * This generates a HW chip id depending on an index, as found on a 162 * two socket system with dual chip modules : 163 * 164 * 0x0, 0x1, 0x10, 0x11 165 * 166 * 4 chips should be the maximum 167 * 168 * TODO: use a machine property to define the chip ids 169 */ 170 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 171 172 /* 173 * Converts back a HW chip id to an index. This is useful to calculate 174 * the MMIO addresses of some controllers which depend on the chip id. 175 */ 176 #define PNV_CHIP_INDEX(chip) \ 177 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 178 179 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 180 181 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 182 #define PNV_MACHINE(obj) \ 183 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 184 #define PNV_MACHINE_GET_CLASS(obj) \ 185 OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) 186 #define PNV_MACHINE_CLASS(klass) \ 187 OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) 188 189 typedef struct PnvMachineState PnvMachineState; 190 191 typedef struct PnvMachineClass { 192 /*< private >*/ 193 MachineClass parent_class; 194 195 /*< public >*/ 196 const char *compat; 197 int compat_size; 198 199 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 200 } PnvMachineClass; 201 202 struct PnvMachineState { 203 /*< private >*/ 204 MachineState parent_obj; 205 206 uint32_t initrd_base; 207 long initrd_size; 208 209 uint32_t num_chips; 210 PnvChip **chips; 211 212 ISABus *isa_bus; 213 uint32_t cpld_irqstate; 214 215 IPMIBmc *bmc; 216 Notifier powerdown_notifier; 217 218 PnvPnor *pnor; 219 }; 220 221 PnvChip *pnv_get_chip(uint32_t chip_id); 222 223 #define PNV_FDT_ADDR 0x01000000 224 #define PNV_TIMEBASE_FREQ 512000000ULL 225 226 /* 227 * BMC helpers 228 */ 229 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 230 void pnv_bmc_powerdown(IPMIBmc *bmc); 231 IPMIBmc *pnv_bmc_create(void); 232 233 /* 234 * POWER8 MMIO base addresses 235 */ 236 #define PNV_XSCOM_SIZE 0x800000000ull 237 #define PNV_XSCOM_BASE(chip) \ 238 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 239 240 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 241 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 242 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 243 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 244 245 #define PNV_HOMER_SIZE 0x0000000000400000ull 246 #define PNV_HOMER_BASE(chip) \ 247 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 248 249 250 /* 251 * XSCOM 0x20109CA defines the ICP BAR: 252 * 253 * 0:29 : bits 14 to 43 of address to define 1 MB region. 254 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 255 * 31:63 : Constant 0 256 * 257 * Usually defined as : 258 * 259 * 0xffffe00200000000 -> 0x0003ffff80000000 260 * 0xffffe00600000000 -> 0x0003ffff80100000 261 * 0xffffe02200000000 -> 0x0003ffff80800000 262 * 0xffffe02600000000 -> 0x0003ffff80900000 263 */ 264 #define PNV_ICP_SIZE 0x0000000000100000ull 265 #define PNV_ICP_BASE(chip) \ 266 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 267 268 269 #define PNV_PSIHB_SIZE 0x0000000000100000ull 270 #define PNV_PSIHB_BASE(chip) \ 271 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 272 273 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 274 #define PNV_PSIHB_FSP_BASE(chip) \ 275 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 276 PNV_PSIHB_FSP_SIZE) 277 278 /* 279 * POWER9 MMIO base addresses 280 */ 281 #define PNV9_CHIP_BASE(chip, base) \ 282 ((base) + ((uint64_t) (chip)->chip_id << 42)) 283 284 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 285 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 286 287 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 288 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 289 290 #define PNV9_LPCM_SIZE 0x0000000100000000ull 291 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 292 293 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 294 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 295 296 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 297 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 298 299 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 300 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 301 302 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 303 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 304 305 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 306 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 307 308 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 309 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 310 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 311 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 312 313 #define PNV9_HOMER_SIZE 0x0000000000400000ull 314 #define PNV9_HOMER_BASE(chip) \ 315 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 316 317 /* 318 * POWER10 MMIO base addresses - 16TB stride per chip 319 */ 320 #define PNV10_CHIP_BASE(chip, base) \ 321 ((base) + ((uint64_t) (chip)->chip_id << 44)) 322 323 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 324 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 325 326 #define PNV10_LPCM_SIZE 0x0000000100000000ull 327 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 328 329 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 330 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 331 332 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 333 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 334 335 #endif /* PPC_PNV_H */ 336