1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef struct PnvChip { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 uint32_t chip_id; 47 uint64_t ram_start; 48 uint64_t ram_size; 49 50 uint32_t nr_cores; 51 uint32_t nr_threads; 52 uint64_t cores_mask; 53 PnvCore **cores; 54 55 MemoryRegion xscom_mmio; 56 MemoryRegion xscom; 57 AddressSpace xscom_as; 58 59 gchar *dt_isa_nodename; 60 } PnvChip; 61 62 #define TYPE_PNV8_CHIP "pnv8-chip" 63 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 64 65 typedef struct Pnv8Chip { 66 /*< private >*/ 67 PnvChip parent_obj; 68 69 /*< public >*/ 70 MemoryRegion icp_mmio; 71 72 PnvLpcController lpc; 73 Pnv8Psi psi; 74 PnvOCC occ; 75 PnvHomer homer; 76 77 XICSFabric *xics; 78 } Pnv8Chip; 79 80 #define TYPE_PNV9_CHIP "pnv9-chip" 81 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 82 83 typedef struct Pnv9Chip { 84 /*< private >*/ 85 PnvChip parent_obj; 86 87 /*< public >*/ 88 PnvXive xive; 89 Pnv9Psi psi; 90 PnvLpcController lpc; 91 PnvOCC occ; 92 PnvHomer homer; 93 94 uint32_t nr_quads; 95 PnvQuad *quads; 96 } Pnv9Chip; 97 98 /* 99 * A SMT8 fused core is a pair of SMT4 cores. 100 */ 101 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 102 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 103 104 #define TYPE_PNV10_CHIP "pnv10-chip" 105 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 106 107 typedef struct Pnv10Chip { 108 /*< private >*/ 109 PnvChip parent_obj; 110 111 /*< public >*/ 112 Pnv9Psi psi; 113 PnvLpcController lpc; 114 } Pnv10Chip; 115 116 typedef struct PnvChipClass { 117 /*< private >*/ 118 SysBusDeviceClass parent_class; 119 120 /*< public >*/ 121 uint64_t chip_cfam_id; 122 uint64_t cores_mask; 123 124 DeviceRealize parent_realize; 125 126 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 127 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 128 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 129 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 130 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 131 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 132 void (*dt_populate)(PnvChip *chip, void *fdt); 133 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 134 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 135 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 136 } PnvChipClass; 137 138 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 139 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 140 141 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 142 #define PNV_CHIP_POWER8E(obj) \ 143 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 144 145 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 146 #define PNV_CHIP_POWER8(obj) \ 147 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 148 149 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 150 #define PNV_CHIP_POWER8NVL(obj) \ 151 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 152 153 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 154 #define PNV_CHIP_POWER9(obj) \ 155 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 156 157 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 158 #define PNV_CHIP_POWER10(obj) \ 159 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 160 161 /* 162 * This generates a HW chip id depending on an index, as found on a 163 * two socket system with dual chip modules : 164 * 165 * 0x0, 0x1, 0x10, 0x11 166 * 167 * 4 chips should be the maximum 168 * 169 * TODO: use a machine property to define the chip ids 170 */ 171 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 172 173 /* 174 * Converts back a HW chip id to an index. This is useful to calculate 175 * the MMIO addresses of some controllers which depend on the chip id. 176 */ 177 #define PNV_CHIP_INDEX(chip) \ 178 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 179 180 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 181 182 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 183 #define PNV_MACHINE(obj) \ 184 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 185 #define PNV_MACHINE_GET_CLASS(obj) \ 186 OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) 187 #define PNV_MACHINE_CLASS(klass) \ 188 OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) 189 190 typedef struct PnvMachineState PnvMachineState; 191 192 typedef struct PnvMachineClass { 193 /*< private >*/ 194 MachineClass parent_class; 195 196 /*< public >*/ 197 const char *compat; 198 int compat_size; 199 200 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 201 } PnvMachineClass; 202 203 struct PnvMachineState { 204 /*< private >*/ 205 MachineState parent_obj; 206 207 uint32_t initrd_base; 208 long initrd_size; 209 210 uint32_t num_chips; 211 PnvChip **chips; 212 213 ISABus *isa_bus; 214 uint32_t cpld_irqstate; 215 216 IPMIBmc *bmc; 217 Notifier powerdown_notifier; 218 219 PnvPnor *pnor; 220 }; 221 222 #define PNV_FDT_ADDR 0x01000000 223 #define PNV_TIMEBASE_FREQ 512000000ULL 224 225 /* 226 * BMC helpers 227 */ 228 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 229 void pnv_bmc_powerdown(IPMIBmc *bmc); 230 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 231 232 /* 233 * POWER8 MMIO base addresses 234 */ 235 #define PNV_XSCOM_SIZE 0x800000000ull 236 #define PNV_XSCOM_BASE(chip) \ 237 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 238 239 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 240 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 241 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 242 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 243 244 #define PNV_HOMER_SIZE 0x0000000000400000ull 245 #define PNV_HOMER_BASE(chip) \ 246 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 247 248 249 /* 250 * XSCOM 0x20109CA defines the ICP BAR: 251 * 252 * 0:29 : bits 14 to 43 of address to define 1 MB region. 253 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 254 * 31:63 : Constant 0 255 * 256 * Usually defined as : 257 * 258 * 0xffffe00200000000 -> 0x0003ffff80000000 259 * 0xffffe00600000000 -> 0x0003ffff80100000 260 * 0xffffe02200000000 -> 0x0003ffff80800000 261 * 0xffffe02600000000 -> 0x0003ffff80900000 262 */ 263 #define PNV_ICP_SIZE 0x0000000000100000ull 264 #define PNV_ICP_BASE(chip) \ 265 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 266 267 268 #define PNV_PSIHB_SIZE 0x0000000000100000ull 269 #define PNV_PSIHB_BASE(chip) \ 270 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 271 272 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 273 #define PNV_PSIHB_FSP_BASE(chip) \ 274 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 275 PNV_PSIHB_FSP_SIZE) 276 277 /* 278 * POWER9 MMIO base addresses 279 */ 280 #define PNV9_CHIP_BASE(chip, base) \ 281 ((base) + ((uint64_t) (chip)->chip_id << 42)) 282 283 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 284 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 285 286 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 287 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 288 289 #define PNV9_LPCM_SIZE 0x0000000100000000ull 290 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 291 292 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 293 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 294 295 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 296 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 297 298 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 299 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 300 301 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 302 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 303 304 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 305 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 306 307 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 308 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 309 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 310 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 311 312 #define PNV9_HOMER_SIZE 0x0000000000400000ull 313 #define PNV9_HOMER_BASE(chip) \ 314 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 315 316 /* 317 * POWER10 MMIO base addresses - 16TB stride per chip 318 */ 319 #define PNV10_CHIP_BASE(chip, base) \ 320 ((base) + ((uint64_t) (chip)->chip_id << 44)) 321 322 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 323 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 324 325 #define PNV10_LPCM_SIZE 0x0000000100000000ull 326 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 327 328 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 329 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 330 331 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 332 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 333 334 #endif /* PPC_PNV_H */ 335