1 #ifndef OPENPIC_H 2 #define OPENPIC_H 3 4 #include "hw/sysbus.h" 5 #include "hw/core/cpu.h" 6 7 #define MAX_CPU 32 8 #define MAX_MSI 8 9 #define VID 0x03 /* MPIC version ID */ 10 11 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ 12 enum { 13 OPENPIC_OUTPUT_INT = 0, /* IRQ */ 14 OPENPIC_OUTPUT_CINT, /* critical IRQ */ 15 OPENPIC_OUTPUT_MCK, /* Machine check event */ 16 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ 17 OPENPIC_OUTPUT_RESET, /* Core reset event */ 18 OPENPIC_OUTPUT_NB, 19 }; 20 21 typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines; 22 23 #define OPENPIC_MODEL_RAVEN 0 24 #define OPENPIC_MODEL_FSL_MPIC_20 1 25 #define OPENPIC_MODEL_FSL_MPIC_42 2 26 #define OPENPIC_MODEL_KEYLARGO 3 27 28 #define OPENPIC_MAX_SRC 256 29 #define OPENPIC_MAX_TMR 4 30 #define OPENPIC_MAX_IPI 4 31 #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \ 32 OPENPIC_MAX_TMR) 33 34 /* Raven */ 35 #define RAVEN_MAX_CPU 2 36 #define RAVEN_MAX_EXT 48 37 #define RAVEN_MAX_IRQ 64 38 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR 39 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI 40 41 /* KeyLargo */ 42 #define KEYLARGO_MAX_CPU 4 43 #define KEYLARGO_MAX_EXT 64 44 #define KEYLARGO_MAX_IPI 4 45 #define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) 46 #define KEYLARGO_MAX_TMR 0 47 #define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ 48 /* Timers don't exist but this makes the code happy... */ 49 #define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) 50 51 /* Interrupt definitions */ 52 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ 53 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ 54 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ 55 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ 56 /* First doorbell IRQ */ 57 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) 58 59 typedef struct FslMpicInfo { 60 int max_ext; 61 } FslMpicInfo; 62 63 typedef enum IRQType { 64 IRQ_TYPE_NORMAL = 0, 65 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ 66 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ 67 } IRQType; 68 69 /* Round up to the nearest 64 IRQs so that the queue length 70 * won't change when moving between 32 and 64 bit hosts. 71 */ 72 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) 73 74 typedef struct IRQQueue { 75 unsigned long *queue; 76 int32_t queue_size; /* Only used for VMSTATE_BITMAP */ 77 int next; 78 int priority; 79 } IRQQueue; 80 81 typedef struct IRQSource { 82 uint32_t ivpr; /* IRQ vector/priority register */ 83 uint32_t idr; /* IRQ destination register */ 84 uint32_t destmask; /* bitmap of CPU destinations */ 85 int last_cpu; 86 int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ 87 int pending; /* TRUE if IRQ is pending */ 88 IRQType type; 89 bool level:1; /* level-triggered */ 90 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ 91 } IRQSource; 92 93 #define IVPR_MASK_SHIFT 31 94 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) 95 #define IVPR_ACTIVITY_SHIFT 30 96 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) 97 #define IVPR_MODE_SHIFT 29 98 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) 99 #define IVPR_POLARITY_SHIFT 23 100 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) 101 #define IVPR_SENSE_SHIFT 22 102 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) 103 104 #define IVPR_PRIORITY_MASK (0xFU << 16) 105 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) 106 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) 107 108 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ 109 #define IDR_EP 0x80000000 /* external pin */ 110 #define IDR_CI 0x40000000 /* critical interrupt */ 111 112 typedef struct OpenPICTimer { 113 uint32_t tccr; /* Global timer current count register */ 114 uint32_t tbcr; /* Global timer base count register */ 115 int n_IRQ; 116 bool qemu_timer_active; /* Is the qemu_timer is running? */ 117 struct QEMUTimer *qemu_timer; 118 struct OpenPICState *opp; /* Device timer is part of. */ 119 /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last 120 current_count written or read, only defined if qemu_timer_active. */ 121 uint64_t origin_time; 122 } OpenPICTimer; 123 124 typedef struct OpenPICMSI { 125 uint32_t msir; /* Shared Message Signaled Interrupt Register */ 126 } OpenPICMSI; 127 128 typedef struct IRQDest { 129 int32_t ctpr; /* CPU current task priority */ 130 IRQQueue raised; 131 IRQQueue servicing; 132 qemu_irq *irqs; 133 134 /* Count of IRQ sources asserting on non-INT outputs */ 135 uint32_t outputs_active[OPENPIC_OUTPUT_NB]; 136 } IRQDest; 137 138 #define TYPE_OPENPIC "openpic" 139 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) 140 141 typedef struct OpenPICState { 142 /*< private >*/ 143 SysBusDevice parent_obj; 144 /*< public >*/ 145 146 MemoryRegion mem; 147 148 /* Behavior control */ 149 FslMpicInfo *fsl; 150 uint32_t model; 151 uint32_t flags; 152 uint32_t nb_irqs; 153 uint32_t vid; 154 uint32_t vir; /* Vendor identification register */ 155 uint32_t vector_mask; 156 uint32_t tfrr_reset; 157 uint32_t ivpr_reset; 158 uint32_t idr_reset; 159 uint32_t brr1; 160 uint32_t mpic_mode_mask; 161 162 /* Sub-regions */ 163 MemoryRegion sub_io_mem[6]; 164 165 /* Global registers */ 166 uint32_t frr; /* Feature reporting register */ 167 uint32_t gcr; /* Global configuration register */ 168 uint32_t pir; /* Processor initialization register */ 169 uint32_t spve; /* Spurious vector register */ 170 uint32_t tfrr; /* Timer frequency reporting register */ 171 /* Source registers */ 172 IRQSource src[OPENPIC_MAX_IRQ]; 173 /* Local registers per output pin */ 174 IRQDest dst[MAX_CPU]; 175 uint32_t nb_cpus; 176 /* Timer registers */ 177 OpenPICTimer timers[OPENPIC_MAX_TMR]; 178 uint32_t max_tmr; 179 180 /* Shared MSI registers */ 181 OpenPICMSI msi[MAX_MSI]; 182 uint32_t max_irq; 183 uint32_t irq_ipi0; 184 uint32_t irq_tim0; 185 uint32_t irq_msi; 186 } OpenPICState; 187 188 #endif /* OPENPIC_H */ 189