1 #ifndef OPENPIC_H 2 #define OPENPIC_H 3 4 #include "qemu-common.h" 5 #include "hw/sysbus.h" 6 #include "hw/qdev-core.h" 7 #include "qom/cpu.h" 8 9 #define MAX_CPU 32 10 #define MAX_MSI 8 11 #define VID 0x03 /* MPIC version ID */ 12 13 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ 14 enum { 15 OPENPIC_OUTPUT_INT = 0, /* IRQ */ 16 OPENPIC_OUTPUT_CINT, /* critical IRQ */ 17 OPENPIC_OUTPUT_MCK, /* Machine check event */ 18 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ 19 OPENPIC_OUTPUT_RESET, /* Core reset event */ 20 OPENPIC_OUTPUT_NB, 21 }; 22 23 typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines; 24 25 #define OPENPIC_MODEL_RAVEN 0 26 #define OPENPIC_MODEL_FSL_MPIC_20 1 27 #define OPENPIC_MODEL_FSL_MPIC_42 2 28 #define OPENPIC_MODEL_KEYLARGO 3 29 30 #define OPENPIC_MAX_SRC 256 31 #define OPENPIC_MAX_TMR 4 32 #define OPENPIC_MAX_IPI 4 33 #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \ 34 OPENPIC_MAX_TMR) 35 36 /* Raven */ 37 #define RAVEN_MAX_CPU 2 38 #define RAVEN_MAX_EXT 48 39 #define RAVEN_MAX_IRQ 64 40 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR 41 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI 42 43 /* KeyLargo */ 44 #define KEYLARGO_MAX_CPU 4 45 #define KEYLARGO_MAX_EXT 64 46 #define KEYLARGO_MAX_IPI 4 47 #define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) 48 #define KEYLARGO_MAX_TMR 0 49 #define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ 50 /* Timers don't exist but this makes the code happy... */ 51 #define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) 52 53 /* Interrupt definitions */ 54 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ 55 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ 56 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ 57 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ 58 /* First doorbell IRQ */ 59 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) 60 61 typedef struct FslMpicInfo { 62 int max_ext; 63 } FslMpicInfo; 64 65 typedef enum IRQType { 66 IRQ_TYPE_NORMAL = 0, 67 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ 68 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ 69 } IRQType; 70 71 /* Round up to the nearest 64 IRQs so that the queue length 72 * won't change when moving between 32 and 64 bit hosts. 73 */ 74 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) 75 76 typedef struct IRQQueue { 77 unsigned long *queue; 78 int32_t queue_size; /* Only used for VMSTATE_BITMAP */ 79 int next; 80 int priority; 81 } IRQQueue; 82 83 typedef struct IRQSource { 84 uint32_t ivpr; /* IRQ vector/priority register */ 85 uint32_t idr; /* IRQ destination register */ 86 uint32_t destmask; /* bitmap of CPU destinations */ 87 int last_cpu; 88 int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ 89 int pending; /* TRUE if IRQ is pending */ 90 IRQType type; 91 bool level:1; /* level-triggered */ 92 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ 93 } IRQSource; 94 95 #define IVPR_MASK_SHIFT 31 96 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) 97 #define IVPR_ACTIVITY_SHIFT 30 98 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) 99 #define IVPR_MODE_SHIFT 29 100 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) 101 #define IVPR_POLARITY_SHIFT 23 102 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) 103 #define IVPR_SENSE_SHIFT 22 104 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) 105 106 #define IVPR_PRIORITY_MASK (0xFU << 16) 107 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) 108 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) 109 110 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ 111 #define IDR_EP 0x80000000 /* external pin */ 112 #define IDR_CI 0x40000000 /* critical interrupt */ 113 114 typedef struct OpenPICTimer { 115 uint32_t tccr; /* Global timer current count register */ 116 uint32_t tbcr; /* Global timer base count register */ 117 int n_IRQ; 118 bool qemu_timer_active; /* Is the qemu_timer is running? */ 119 struct QEMUTimer *qemu_timer; 120 struct OpenPICState *opp; /* Device timer is part of. */ 121 /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last 122 current_count written or read, only defined if qemu_timer_active. */ 123 uint64_t origin_time; 124 } OpenPICTimer; 125 126 typedef struct OpenPICMSI { 127 uint32_t msir; /* Shared Message Signaled Interrupt Register */ 128 } OpenPICMSI; 129 130 typedef struct IRQDest { 131 int32_t ctpr; /* CPU current task priority */ 132 IRQQueue raised; 133 IRQQueue servicing; 134 qemu_irq *irqs; 135 136 /* Count of IRQ sources asserting on non-INT outputs */ 137 uint32_t outputs_active[OPENPIC_OUTPUT_NB]; 138 } IRQDest; 139 140 #define TYPE_OPENPIC "openpic" 141 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) 142 143 typedef struct OpenPICState { 144 /*< private >*/ 145 SysBusDevice parent_obj; 146 /*< public >*/ 147 148 MemoryRegion mem; 149 150 /* Behavior control */ 151 FslMpicInfo *fsl; 152 uint32_t model; 153 uint32_t flags; 154 uint32_t nb_irqs; 155 uint32_t vid; 156 uint32_t vir; /* Vendor identification register */ 157 uint32_t vector_mask; 158 uint32_t tfrr_reset; 159 uint32_t ivpr_reset; 160 uint32_t idr_reset; 161 uint32_t brr1; 162 uint32_t mpic_mode_mask; 163 164 /* Sub-regions */ 165 MemoryRegion sub_io_mem[6]; 166 167 /* Global registers */ 168 uint32_t frr; /* Feature reporting register */ 169 uint32_t gcr; /* Global configuration register */ 170 uint32_t pir; /* Processor initialization register */ 171 uint32_t spve; /* Spurious vector register */ 172 uint32_t tfrr; /* Timer frequency reporting register */ 173 /* Source registers */ 174 IRQSource src[OPENPIC_MAX_IRQ]; 175 /* Local registers per output pin */ 176 IRQDest dst[MAX_CPU]; 177 uint32_t nb_cpus; 178 /* Timer registers */ 179 OpenPICTimer timers[OPENPIC_MAX_TMR]; 180 uint32_t max_tmr; 181 182 /* Shared MSI registers */ 183 OpenPICMSI msi[MAX_MSI]; 184 uint32_t max_irq; 185 uint32_t irq_ipi0; 186 uint32_t irq_tim0; 187 uint32_t irq_msi; 188 } OpenPICState; 189 190 #endif /* OPENPIC_H */ 191