1 /* 2 * Copyright (c) 2009 Laurent Vivier 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 #ifndef HW_MAC_DBDMA_H 23 #define HW_MAC_DBDMA_H 1 24 25 #include "exec/memory.h" 26 #include "qemu/iov.h" 27 28 typedef struct DBDMA_io DBDMA_io; 29 30 typedef void (*DBDMA_flush)(DBDMA_io *io); 31 typedef void (*DBDMA_rw)(DBDMA_io *io); 32 typedef void (*DBDMA_end)(DBDMA_io *io); 33 struct DBDMA_io { 34 void *opaque; 35 void *channel; 36 hwaddr addr; 37 int len; 38 int is_last; 39 int is_dma_out; 40 DBDMA_end dma_end; 41 /* DMA is in progress, don't start another one */ 42 bool processing; 43 /* unaligned last sector of a request */ 44 uint8_t head_remainder[0x200]; 45 uint8_t tail_remainder[0x200]; 46 QEMUIOVector iov; 47 }; 48 49 /* 50 * DBDMA control/status registers. All little-endian. 51 */ 52 53 #define DBDMA_CONTROL 0x00 54 #define DBDMA_STATUS 0x01 55 #define DBDMA_CMDPTR_HI 0x02 56 #define DBDMA_CMDPTR_LO 0x03 57 #define DBDMA_INTR_SEL 0x04 58 #define DBDMA_BRANCH_SEL 0x05 59 #define DBDMA_WAIT_SEL 0x06 60 #define DBDMA_XFER_MODE 0x07 61 #define DBDMA_DATA2PTR_HI 0x08 62 #define DBDMA_DATA2PTR_LO 0x09 63 #define DBDMA_RES1 0x0A 64 #define DBDMA_ADDRESS_HI 0x0B 65 #define DBDMA_BRANCH_ADDR_HI 0x0C 66 #define DBDMA_RES2 0x0D 67 #define DBDMA_RES3 0x0E 68 #define DBDMA_RES4 0x0F 69 70 #define DBDMA_REGS 16 71 #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) 72 73 #define DBDMA_CHANNEL_SHIFT 7 74 #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) 75 76 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) 77 78 /* Bits in control and status registers */ 79 80 #define RUN 0x8000 81 #define PAUSE 0x4000 82 #define FLUSH 0x2000 83 #define WAKE 0x1000 84 #define DEAD 0x0800 85 #define ACTIVE 0x0400 86 #define BT 0x0100 87 #define DEVSTAT 0x00ff 88 89 /* 90 * DBDMA command structure. These fields are all little-endian! 91 */ 92 93 typedef struct dbdma_cmd { 94 uint16_t req_count; /* requested byte transfer count */ 95 uint16_t command; /* command word (has bit-fields) */ 96 uint32_t phy_addr; /* physical data address */ 97 uint32_t cmd_dep; /* command-dependent field */ 98 uint16_t res_count; /* residual count after completion */ 99 uint16_t xfer_status; /* transfer status */ 100 } dbdma_cmd; 101 102 /* DBDMA command values in command field */ 103 104 #define COMMAND_MASK 0xf000 105 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ 106 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ 107 #define INPUT_MORE 0x2000 /* transfer stream data to memory */ 108 #define INPUT_LAST 0x3000 /* ditto, expect end marker */ 109 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ 110 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ 111 #define DBDMA_NOP 0x6000 /* do nothing */ 112 #define DBDMA_STOP 0x7000 /* suspend processing */ 113 114 /* Key values in command field */ 115 116 #define KEY_MASK 0x0700 117 #define KEY_STREAM0 0x0000 /* usual data stream */ 118 #define KEY_STREAM1 0x0100 /* control/status stream */ 119 #define KEY_STREAM2 0x0200 /* device-dependent stream */ 120 #define KEY_STREAM3 0x0300 /* device-dependent stream */ 121 #define KEY_STREAM4 0x0400 /* reserved */ 122 #define KEY_REGS 0x0500 /* device register space */ 123 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ 124 #define KEY_DEVICE 0x0700 /* device memory-mapped space */ 125 126 /* Interrupt control values in command field */ 127 128 #define INTR_MASK 0x0030 129 #define INTR_NEVER 0x0000 /* don't interrupt */ 130 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ 131 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ 132 #define INTR_ALWAYS 0x0030 /* always interrupt */ 133 134 /* Branch control values in command field */ 135 136 #define BR_MASK 0x000c 137 #define BR_NEVER 0x0000 /* don't branch */ 138 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ 139 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ 140 #define BR_ALWAYS 0x000c /* always branch */ 141 142 /* Wait control values in command field */ 143 144 #define WAIT_MASK 0x0003 145 #define WAIT_NEVER 0x0000 /* don't wait */ 146 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ 147 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ 148 #define WAIT_ALWAYS 0x0003 /* always wait */ 149 150 typedef struct DBDMA_channel { 151 int channel; 152 uint32_t regs[DBDMA_REGS]; 153 qemu_irq irq; 154 DBDMA_io io; 155 DBDMA_rw rw; 156 DBDMA_flush flush; 157 dbdma_cmd current; 158 } DBDMA_channel; 159 160 typedef struct { 161 MemoryRegion mem; 162 DBDMA_channel channels[DBDMA_CHANNELS]; 163 QEMUBH *bh; 164 } DBDMAState; 165 166 /* Externally callable functions */ 167 168 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, 169 DBDMA_rw rw, DBDMA_flush flush, 170 void *opaque); 171 void DBDMA_kick(DBDMAState *dbdma); 172 void* DBDMA_init (MemoryRegion **dbdma_mem); 173 174 #endif 175