1 /* 2 * Copyright (c) 2009 Laurent Vivier 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 #ifndef HW_MAC_DBDMA_H 23 #define HW_MAC_DBDMA_H 1 24 25 #include "exec/memory.h" 26 27 typedef struct DBDMA_io DBDMA_io; 28 29 typedef void (*DBDMA_flush)(DBDMA_io *io); 30 typedef void (*DBDMA_rw)(DBDMA_io *io); 31 typedef void (*DBDMA_end)(DBDMA_io *io); 32 struct DBDMA_io { 33 void *opaque; 34 void *channel; 35 hwaddr addr; 36 int len; 37 int is_last; 38 int is_dma_out; 39 DBDMA_end dma_end; 40 /* DMA is in progress, don't start another one */ 41 bool processing; 42 }; 43 44 /* 45 * DBDMA control/status registers. All little-endian. 46 */ 47 48 #define DBDMA_CONTROL 0x00 49 #define DBDMA_STATUS 0x01 50 #define DBDMA_CMDPTR_HI 0x02 51 #define DBDMA_CMDPTR_LO 0x03 52 #define DBDMA_INTR_SEL 0x04 53 #define DBDMA_BRANCH_SEL 0x05 54 #define DBDMA_WAIT_SEL 0x06 55 #define DBDMA_XFER_MODE 0x07 56 #define DBDMA_DATA2PTR_HI 0x08 57 #define DBDMA_DATA2PTR_LO 0x09 58 #define DBDMA_RES1 0x0A 59 #define DBDMA_ADDRESS_HI 0x0B 60 #define DBDMA_BRANCH_ADDR_HI 0x0C 61 #define DBDMA_RES2 0x0D 62 #define DBDMA_RES3 0x0E 63 #define DBDMA_RES4 0x0F 64 65 #define DBDMA_REGS 16 66 #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) 67 68 #define DBDMA_CHANNEL_SHIFT 7 69 #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) 70 71 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) 72 73 /* Bits in control and status registers */ 74 75 #define RUN 0x8000 76 #define PAUSE 0x4000 77 #define FLUSH 0x2000 78 #define WAKE 0x1000 79 #define DEAD 0x0800 80 #define ACTIVE 0x0400 81 #define BT 0x0100 82 #define DEVSTAT 0x00ff 83 84 /* 85 * DBDMA command structure. These fields are all little-endian! 86 */ 87 88 typedef struct dbdma_cmd { 89 uint16_t req_count; /* requested byte transfer count */ 90 uint16_t command; /* command word (has bit-fields) */ 91 uint32_t phy_addr; /* physical data address */ 92 uint32_t cmd_dep; /* command-dependent field */ 93 uint16_t res_count; /* residual count after completion */ 94 uint16_t xfer_status; /* transfer status */ 95 } dbdma_cmd; 96 97 /* DBDMA command values in command field */ 98 99 #define COMMAND_MASK 0xf000 100 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ 101 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ 102 #define INPUT_MORE 0x2000 /* transfer stream data to memory */ 103 #define INPUT_LAST 0x3000 /* ditto, expect end marker */ 104 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ 105 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ 106 #define DBDMA_NOP 0x6000 /* do nothing */ 107 #define DBDMA_STOP 0x7000 /* suspend processing */ 108 109 /* Key values in command field */ 110 111 #define KEY_MASK 0x0700 112 #define KEY_STREAM0 0x0000 /* usual data stream */ 113 #define KEY_STREAM1 0x0100 /* control/status stream */ 114 #define KEY_STREAM2 0x0200 /* device-dependent stream */ 115 #define KEY_STREAM3 0x0300 /* device-dependent stream */ 116 #define KEY_STREAM4 0x0400 /* reserved */ 117 #define KEY_REGS 0x0500 /* device register space */ 118 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ 119 #define KEY_DEVICE 0x0700 /* device memory-mapped space */ 120 121 /* Interrupt control values in command field */ 122 123 #define INTR_MASK 0x0030 124 #define INTR_NEVER 0x0000 /* don't interrupt */ 125 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ 126 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ 127 #define INTR_ALWAYS 0x0030 /* always interrupt */ 128 129 /* Branch control values in command field */ 130 131 #define BR_MASK 0x000c 132 #define BR_NEVER 0x0000 /* don't branch */ 133 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ 134 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ 135 #define BR_ALWAYS 0x000c /* always branch */ 136 137 /* Wait control values in command field */ 138 139 #define WAIT_MASK 0x0003 140 #define WAIT_NEVER 0x0000 /* don't wait */ 141 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ 142 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ 143 #define WAIT_ALWAYS 0x0003 /* always wait */ 144 145 typedef struct DBDMA_channel { 146 int channel; 147 uint32_t regs[DBDMA_REGS]; 148 qemu_irq irq; 149 DBDMA_io io; 150 DBDMA_rw rw; 151 DBDMA_flush flush; 152 dbdma_cmd current; 153 } DBDMA_channel; 154 155 typedef struct { 156 MemoryRegion mem; 157 DBDMA_channel channels[DBDMA_CHANNELS]; 158 QEMUBH *bh; 159 } DBDMAState; 160 161 /* Externally callable functions */ 162 163 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, 164 DBDMA_rw rw, DBDMA_flush flush, 165 void *opaque); 166 void DBDMA_kick(DBDMAState *dbdma); 167 void* DBDMA_init (MemoryRegion **dbdma_mem); 168 169 #endif 170