xref: /openbmc/qemu/include/hw/pci/shpc.h (revision 7c08eefc)
1 #ifndef SHPC_H
2 #define SHPC_H
3 
4 #include "exec/memory.h"
5 #include "hw/hotplug.h"
6 #include "hw/pci/pci_device.h"
7 #include "migration/vmstate.h"
8 
9 struct SHPCDevice {
10     /* Capability offset in device's config space */
11     int cap;
12 
13     /* # of hot-pluggable slots */
14     int nslots;
15 
16     /* SHPC WRS: working register set */
17     uint8_t *config;
18 
19     /* Used to enable checks on load. Note that writable bits are
20      * never checked even if set in cmask. */
21     uint8_t *cmask;
22 
23     /* Used to implement R/W bytes */
24     uint8_t *wmask;
25 
26     /* Used to implement RW1C(Write 1 to Clear) bytes */
27     uint8_t *w1cmask;
28 
29     /* MMIO for the SHPC BAR */
30     MemoryRegion mmio;
31 
32     /* Bus controlled by this SHPC */
33     PCIBus *sec_bus;
34 
35     /* MSI already requested for this event */
36     int msi_requested;
37 };
38 
39 void shpc_reset(PCIDevice *d);
40 int shpc_bar_size(PCIDevice *dev);
41 int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar,
42               unsigned off, Error **errp);
43 void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
44 void shpc_free(PCIDevice *dev);
45 void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
46 
47 
48 void shpc_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
49                          Error **errp);
50 void shpc_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
51                            Error **errp);
52 void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
53                                    DeviceState *dev, Error **errp);
54 
55 extern const VMStateInfo shpc_vmstate_info;
56 #define SHPC_VMSTATE(_field, _type,  _test) \
57     VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _type, _test, 0, \
58                                     shpc_vmstate_info, 0)
59 
60 static inline bool shpc_present(const PCIDevice *dev)
61 {
62     return dev->cap_present & QEMU_PCI_CAP_SHPC;
63 }
64 
65 #endif
66