1 /* 2 * PCIe Data Object Exchange 3 * 4 * Copyright (C) 2021 Avery Design Systems, Inc. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCIE_DOE_H 11 #define PCIE_DOE_H 12 13 #include "qemu/range.h" 14 #include "qemu/typedefs.h" 15 #include "hw/register.h" 16 17 /* 18 * Reference: 19 * PCIe r6.0 - 7.9.24 Data Object Exchange Extended Capability 20 */ 21 /* Capabilities Register - r6.0 7.9.24.2 */ 22 #define PCI_EXP_DOE_CAP 0x04 23 REG32(PCI_DOE_CAP_REG, 0) 24 FIELD(PCI_DOE_CAP_REG, INTR_SUPP, 0, 1) 25 FIELD(PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, 1, 11) 26 27 /* Control Register - r6.0 7.9.24.3 */ 28 #define PCI_EXP_DOE_CTRL 0x08 29 REG32(PCI_DOE_CAP_CONTROL, 0) 30 FIELD(PCI_DOE_CAP_CONTROL, DOE_ABORT, 0, 1) 31 FIELD(PCI_DOE_CAP_CONTROL, DOE_INTR_EN, 1, 1) 32 FIELD(PCI_DOE_CAP_CONTROL, DOE_GO, 31, 1) 33 34 /* Status Register - r6.0 7.9.24.4 */ 35 #define PCI_EXP_DOE_STATUS 0x0c 36 REG32(PCI_DOE_CAP_STATUS, 0) 37 FIELD(PCI_DOE_CAP_STATUS, DOE_BUSY, 0, 1) 38 FIELD(PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, 1, 1) 39 FIELD(PCI_DOE_CAP_STATUS, DOE_ERROR, 2, 1) 40 FIELD(PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, 31, 1) 41 42 /* Write Data Mailbox Register - r6.0 7.9.24.5 */ 43 #define PCI_EXP_DOE_WR_DATA_MBOX 0x10 44 45 /* Read Data Mailbox Register - 7.9.xx.6 */ 46 #define PCI_EXP_DOE_RD_DATA_MBOX 0x14 47 48 /* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */ 49 #define PCI_SIG_DOE_DISCOVERY 0x00 50 51 #define PCI_DOE_DW_SIZE_MAX (1 << 18) 52 #define PCI_DOE_PROTOCOL_NUM_MAX 256 53 54 #define DATA_OBJ_BUILD_HEADER1(v, p) (((p) << 16) | (v)) 55 #define DATA_OBJ_LEN_MASK(len) ((len) & (PCI_DOE_DW_SIZE_MAX - 1)) 56 57 typedef struct DOEHeader DOEHeader; 58 typedef struct DOEProtocol DOEProtocol; 59 typedef struct DOECap DOECap; 60 61 struct DOEHeader { 62 uint16_t vendor_id; 63 uint8_t data_obj_type; 64 uint8_t reserved; 65 uint32_t length; 66 } QEMU_PACKED; 67 68 /* Protocol infos and rsp function callback */ 69 struct DOEProtocol { 70 uint16_t vendor_id; 71 uint8_t data_obj_type; 72 bool (*handle_request)(DOECap *); 73 }; 74 75 struct DOECap { 76 /* Owner */ 77 PCIDevice *pdev; 78 79 uint16_t offset; 80 81 struct { 82 bool intr; 83 uint16_t vec; 84 } cap; 85 86 struct { 87 bool abort; 88 bool intr; 89 bool go; 90 } ctrl; 91 92 struct { 93 bool busy; 94 bool intr; 95 bool error; 96 bool ready; 97 } status; 98 99 uint32_t *write_mbox; 100 uint32_t *read_mbox; 101 102 /* Mailbox position indicator */ 103 uint32_t read_mbox_idx; 104 uint32_t read_mbox_len; 105 uint32_t write_mbox_len; 106 107 /* Protocols and its callback response */ 108 DOEProtocol *protocols; 109 uint16_t protocol_num; 110 }; 111 112 void pcie_doe_init(PCIDevice *pdev, DOECap *doe_cap, uint16_t offset, 113 DOEProtocol *protocols, bool intr, uint16_t vec); 114 void pcie_doe_fini(DOECap *doe_cap); 115 bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size, 116 uint32_t *buf); 117 void pcie_doe_write_config(DOECap *doe_cap, uint32_t addr, 118 uint32_t val, int size); 119 uint32_t pcie_doe_build_protocol(DOEProtocol *p); 120 void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap); 121 void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp); 122 uint32_t pcie_doe_get_obj_len(void *obj); 123 #endif /* PCIE_DOE_H */ 124