1 /* 2 * PCIe Data Object Exchange 3 * 4 * Copyright (C) 2021 Avery Design Systems, Inc. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCIE_DOE_H 11 #define PCIE_DOE_H 12 13 #include "qemu/range.h" 14 #include "hw/register.h" 15 16 /* 17 * Reference: 18 * PCIe r6.0 - 7.9.24 Data Object Exchange Extended Capability 19 */ 20 /* Capabilities Register - r6.0 7.9.24.2 */ 21 #define PCI_EXP_DOE_CAP 0x04 22 REG32(PCI_DOE_CAP_REG, 0) 23 FIELD(PCI_DOE_CAP_REG, INTR_SUPP, 0, 1) 24 FIELD(PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, 1, 11) 25 26 /* Control Register - r6.0 7.9.24.3 */ 27 #define PCI_EXP_DOE_CTRL 0x08 28 REG32(PCI_DOE_CAP_CONTROL, 0) 29 FIELD(PCI_DOE_CAP_CONTROL, DOE_ABORT, 0, 1) 30 FIELD(PCI_DOE_CAP_CONTROL, DOE_INTR_EN, 1, 1) 31 FIELD(PCI_DOE_CAP_CONTROL, DOE_GO, 31, 1) 32 33 /* Status Register - r6.0 7.9.24.4 */ 34 #define PCI_EXP_DOE_STATUS 0x0c 35 REG32(PCI_DOE_CAP_STATUS, 0) 36 FIELD(PCI_DOE_CAP_STATUS, DOE_BUSY, 0, 1) 37 FIELD(PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, 1, 1) 38 FIELD(PCI_DOE_CAP_STATUS, DOE_ERROR, 2, 1) 39 FIELD(PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, 31, 1) 40 41 /* Write Data Mailbox Register - r6.0 7.9.24.5 */ 42 #define PCI_EXP_DOE_WR_DATA_MBOX 0x10 43 44 /* Read Data Mailbox Register - 7.9.xx.6 */ 45 #define PCI_EXP_DOE_RD_DATA_MBOX 0x14 46 47 /* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */ 48 #define PCI_SIG_DOE_DISCOVERY 0x00 49 50 #define PCI_DOE_DW_SIZE_MAX (1 << 18) 51 #define PCI_DOE_PROTOCOL_NUM_MAX 256 52 53 #define DATA_OBJ_BUILD_HEADER1(v, p) (((p) << 16) | (v)) 54 #define DATA_OBJ_LEN_MASK(len) ((len) & (PCI_DOE_DW_SIZE_MAX - 1)) 55 56 typedef struct DOEHeader DOEHeader; 57 typedef struct DOEProtocol DOEProtocol; 58 typedef struct DOECap DOECap; 59 60 struct DOEHeader { 61 uint16_t vendor_id; 62 uint8_t data_obj_type; 63 uint8_t reserved; 64 uint32_t length; 65 } QEMU_PACKED; 66 67 /* Protocol infos and rsp function callback */ 68 struct DOEProtocol { 69 uint16_t vendor_id; 70 uint8_t data_obj_type; 71 bool (*handle_request)(DOECap *); 72 }; 73 74 struct DOECap { 75 /* Owner */ 76 PCIDevice *pdev; 77 78 uint16_t offset; 79 80 struct { 81 bool intr; 82 uint16_t vec; 83 } cap; 84 85 struct { 86 bool abort; 87 bool intr; 88 bool go; 89 } ctrl; 90 91 struct { 92 bool busy; 93 bool intr; 94 bool error; 95 bool ready; 96 } status; 97 98 uint32_t *write_mbox; 99 uint32_t *read_mbox; 100 101 /* Mailbox position indicator */ 102 uint32_t read_mbox_idx; 103 uint32_t read_mbox_len; 104 uint32_t write_mbox_len; 105 106 /* Protocols and its callback response */ 107 DOEProtocol *protocols; 108 uint16_t protocol_num; 109 }; 110 111 void pcie_doe_init(PCIDevice *pdev, DOECap *doe_cap, uint16_t offset, 112 DOEProtocol *protocols, bool intr, uint16_t vec); 113 void pcie_doe_fini(DOECap *doe_cap); 114 bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size, 115 uint32_t *buf); 116 void pcie_doe_write_config(DOECap *doe_cap, uint32_t addr, 117 uint32_t val, int size); 118 uint32_t pcie_doe_build_protocol(DOEProtocol *p); 119 void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap); 120 void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp); 121 uint32_t pcie_doe_get_obj_len(void *obj); 122 #endif /* PCIE_DOE_H */ 123