xref: /openbmc/qemu/include/hw/pci/pcie.h (revision e0091133)
1 /*
2  * pcie.h
3  *
4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5  *                    VA Linux Systems Japan K.K.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef QEMU_PCIE_H
22 #define QEMU_PCIE_H
23 
24 #include "hw/pci/pci_regs.h"
25 #include "hw/pci/pcie_regs.h"
26 #include "hw/pci/pcie_aer.h"
27 #include "hw/pci/pcie_sriov.h"
28 #include "hw/hotplug.h"
29 #include "hw/pci/pcie_doe.h"
30 
31 typedef enum {
32     /* for attention and power indicator */
33     PCI_EXP_HP_IND_RESERVED     = PCI_EXP_SLTCTL_IND_RESERVED,
34     PCI_EXP_HP_IND_ON           = PCI_EXP_SLTCTL_IND_ON,
35     PCI_EXP_HP_IND_BLINK        = PCI_EXP_SLTCTL_IND_BLINK,
36     PCI_EXP_HP_IND_OFF          = PCI_EXP_SLTCTL_IND_OFF,
37 } PCIExpressIndicator;
38 
39 typedef enum {
40     /* these bits must match the bits in Slot Control/Status registers.
41      * PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx
42      *
43      * Not all the bits of slot control register match with the ones of
44      * slot status. Not some bits of slot status register is used to
45      * show status, not to report event occurrence.
46      * So such bits must be masked out when checking the software
47      * notification condition.
48      */
49     PCI_EXP_HP_EV_ABP           = PCI_EXP_SLTCTL_ABPE,
50                                         /* attention button pressed */
51     PCI_EXP_HP_EV_PDC           = PCI_EXP_SLTCTL_PDCE,
52                                         /* presence detect changed */
53     PCI_EXP_HP_EV_CCI           = PCI_EXP_SLTCTL_CCIE,
54                                         /* command completed */
55 
56     PCI_EXP_HP_EV_SUPPORTED     = PCI_EXP_HP_EV_ABP |
57                                   PCI_EXP_HP_EV_PDC |
58                                   PCI_EXP_HP_EV_CCI,
59                                                 /* supported event mask  */
60 
61     /* events not listed aren't supported */
62 } PCIExpressHotPlugEvent;
63 
64 struct PCIExpressDevice {
65     /* Offset of express capability in config space */
66     uint8_t exp_cap;
67     /* Offset of Power Management capability in config space */
68     uint8_t pm_cap;
69 
70     /* SLOT */
71     bool hpev_notified; /* Logical AND of conditions for hot plug event.
72                          Following 6.7.3.4:
73                          Software Notification of Hot-Plug Events, an interrupt
74                          is sent whenever the logical and of these conditions
75                          transitions from false to true. */
76 
77     /* AER */
78     uint16_t aer_cap;
79     PCIEAERLog aer_log;
80 
81     /* Offset of ATS capability in config space */
82     uint16_t ats_cap;
83 
84     /* ACS */
85     uint16_t acs_cap;
86 
87     /* SR/IOV */
88     uint16_t sriov_cap;
89     PCIESriovPF sriov_pf;
90     PCIESriovVF sriov_vf;
91 };
92 
93 #define COMPAT_PROP_PCP "power_controller_present"
94 
95 /* PCI express capability helper functions */
96 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type,
97                   uint8_t port, Error **errp);
98 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
99                      uint8_t type, uint8_t port);
100 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
101 void pcie_cap_exit(PCIDevice *dev);
102 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset);
103 void pcie_cap_v1_exit(PCIDevice *dev);
104 uint8_t pcie_cap_get_type(const PCIDevice *dev);
105 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
106 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
107 
108 void pcie_cap_deverr_init(PCIDevice *dev);
109 void pcie_cap_deverr_reset(PCIDevice *dev);
110 
111 void pcie_cap_lnkctl_init(PCIDevice *dev);
112 void pcie_cap_lnkctl_reset(PCIDevice *dev);
113 
114 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s);
115 void pcie_cap_slot_reset(PCIDevice *dev);
116 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
117 void pcie_cap_slot_write_config(PCIDevice *dev,
118                                 uint16_t old_slt_ctl, uint16_t old_slt_sta,
119                                 uint32_t addr, uint32_t val, int len);
120 int pcie_cap_slot_post_load(void *opaque, int version_id);
121 void pcie_cap_slot_push_attention_button(PCIDevice *dev);
122 void pcie_cap_slot_enable_power(PCIDevice *dev);
123 
124 void pcie_cap_root_init(PCIDevice *dev);
125 void pcie_cap_root_reset(PCIDevice *dev);
126 
127 void pcie_cap_flr_init(PCIDevice *dev);
128 void pcie_cap_flr_write_config(PCIDevice *dev,
129                            uint32_t addr, uint32_t val, int len);
130 
131 /* ARI forwarding capability and control */
132 void pcie_cap_arifwd_init(PCIDevice *dev);
133 void pcie_cap_arifwd_reset(PCIDevice *dev);
134 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev);
135 
136 /* PCI express extended capability helper functions */
137 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
138 void pcie_add_capability(PCIDevice *dev,
139                          uint16_t cap_id, uint8_t cap_ver,
140                          uint16_t offset, uint16_t size);
141 void pcie_sync_bridge_lnk(PCIDevice *dev);
142 
143 void pcie_acs_init(PCIDevice *dev, uint16_t offset);
144 void pcie_acs_reset(PCIDevice *dev);
145 
146 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
147 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
148 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned);
149 
150 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
151                                Error **errp);
152 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
153                            Error **errp);
154 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
155                              Error **errp);
156 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
157                                      DeviceState *dev, Error **errp);
158 #endif /* QEMU_PCIE_H */
159