1 #ifndef QEMU_PCI_DEVICE_H
2 #define QEMU_PCI_DEVICE_H
3
4 #include "hw/pci/pci.h"
5 #include "hw/pci/pcie.h"
6 #include "hw/pci/pcie_doe.h"
7
8 #define TYPE_PCI_DEVICE "pci-device"
9 typedef struct PCIDeviceClass PCIDeviceClass;
10 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
11 PCI_DEVICE, TYPE_PCI_DEVICE)
12
13 /*
14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
15 * actually a "CXL Component, but we name it device to match the PCI naming.
16 */
17 #define INTERFACE_CXL_DEVICE "cxl-device"
18
19 /* Implemented by devices that can be plugged on PCI Express buses */
20 #define INTERFACE_PCIE_DEVICE "pci-express-device"
21
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
23 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
24
25 struct PCIDeviceClass {
26 DeviceClass parent_class;
27
28 void (*realize)(PCIDevice *dev, Error **errp);
29 PCIUnregisterFunc *exit;
30 PCIConfigReadFunc *config_read;
31 PCIConfigWriteFunc *config_write;
32
33 uint16_t vendor_id;
34 uint16_t device_id;
35 uint8_t revision;
36 uint16_t class_id;
37 uint16_t subsystem_vendor_id; /* only for header type = 0 */
38 uint16_t subsystem_id; /* only for header type = 0 */
39
40 const char *romfile; /* rom bar */
41 };
42
43 enum PCIReqIDType {
44 PCI_REQ_ID_INVALID = 0,
45 PCI_REQ_ID_BDF,
46 PCI_REQ_ID_SECONDARY_BUS,
47 PCI_REQ_ID_MAX,
48 };
49 typedef enum PCIReqIDType PCIReqIDType;
50
51 struct PCIReqIDCache {
52 PCIDevice *dev;
53 PCIReqIDType type;
54 };
55 typedef struct PCIReqIDCache PCIReqIDCache;
56
57 struct PCIDevice {
58 DeviceState qdev;
59 bool partially_hotplugged;
60 bool has_power;
61
62 /* PCI config space */
63 uint8_t *config;
64
65 /*
66 * Used to enable config checks on load. Note that writable bits are
67 * never checked even if set in cmask.
68 */
69 uint8_t *cmask;
70
71 /* Used to implement R/W bytes */
72 uint8_t *wmask;
73
74 /* Used to implement RW1C(Write 1 to Clear) bytes */
75 uint8_t *w1cmask;
76
77 /* Used to allocate config space for capabilities. */
78 uint8_t *used;
79
80 /* the following fields are read only */
81 int32_t devfn;
82 /*
83 * Cached device to fetch requester ID from, to avoid the PCI tree
84 * walking every time we invoke PCI request (e.g., MSI). For
85 * conventional PCI root complex, this field is meaningless.
86 */
87 PCIReqIDCache requester_id_cache;
88 char name[64];
89 PCIIORegion io_regions[PCI_NUM_REGIONS];
90 AddressSpace bus_master_as;
91 MemoryRegion bus_master_container_region;
92 MemoryRegion bus_master_enable_region;
93
94 /* do not access the following fields */
95 PCIConfigReadFunc *config_read;
96 PCIConfigWriteFunc *config_write;
97
98 /* Legacy PCI VGA regions */
99 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
100 bool has_vga;
101
102 /* Current IRQ levels. Used internally by the generic PCI code. */
103 uint8_t irq_state;
104
105 /* Capability bits */
106 uint32_t cap_present;
107
108 /* Offset of MSI-X capability in config space */
109 uint8_t msix_cap;
110
111 /* MSI-X entries */
112 int msix_entries_nr;
113
114 /* Space to store MSIX table & pending bit array */
115 uint8_t *msix_table;
116 uint8_t *msix_pba;
117
118 /* May be used by INTx or MSI during interrupt notification */
119 void *irq_opaque;
120
121 MSITriggerFunc *msi_trigger;
122 MSIPrepareMessageFunc *msi_prepare_message;
123 MSIxPrepareMessageFunc *msix_prepare_message;
124
125 /* MemoryRegion container for msix exclusive BAR setup */
126 MemoryRegion msix_exclusive_bar;
127 /* Memory Regions for MSIX table and pending bit entries. */
128 MemoryRegion msix_table_mmio;
129 MemoryRegion msix_pba_mmio;
130 /* Reference-count for entries actually in use by driver. */
131 unsigned *msix_entry_used;
132 /* MSIX function mask set or MSIX disabled */
133 bool msix_function_masked;
134 /* Version id needed for VMState */
135 int32_t version_id;
136
137 /* Offset of MSI capability in config space */
138 uint8_t msi_cap;
139
140 /* PCI Express */
141 PCIExpressDevice exp;
142
143 /* SHPC */
144 SHPCDevice *shpc;
145
146 /* Location of option rom */
147 char *romfile;
148 uint32_t romsize;
149 bool has_rom;
150 MemoryRegion rom;
151 uint32_t rom_bar;
152
153 /* INTx routing notifier */
154 PCIINTxRoutingNotifier intx_routing_notifier;
155
156 /* MSI-X notifiers */
157 MSIVectorUseNotifier msix_vector_use_notifier;
158 MSIVectorReleaseNotifier msix_vector_release_notifier;
159 MSIVectorPollNotifier msix_vector_poll_notifier;
160
161 /* SPDM */
162 uint16_t spdm_port;
163
164 /* DOE */
165 DOECap doe_spdm;
166
167 /* ID of standby device in net_failover pair */
168 char *failover_pair_id;
169 uint32_t acpi_index;
170
171 /*
172 * Indirect DMA region bounce buffer size as configured for the device. This
173 * is a configuration parameter that is reflected into bus_master_as when
174 * realizing the device.
175 */
176 uint32_t max_bounce_buffer_size;
177 };
178
pci_intx(PCIDevice * pci_dev)179 static inline int pci_intx(PCIDevice *pci_dev)
180 {
181 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
182 }
183
pci_is_cxl(const PCIDevice * d)184 static inline int pci_is_cxl(const PCIDevice *d)
185 {
186 return d->cap_present & QEMU_PCIE_CAP_CXL;
187 }
188
pci_is_express(const PCIDevice * d)189 static inline int pci_is_express(const PCIDevice *d)
190 {
191 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
192 }
193
pci_is_express_downstream_port(const PCIDevice * d)194 static inline int pci_is_express_downstream_port(const PCIDevice *d)
195 {
196 uint8_t type;
197
198 if (!pci_is_express(d) || !d->exp.exp_cap) {
199 return 0;
200 }
201
202 type = pcie_cap_get_type(d);
203
204 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
205 }
206
pci_is_vf(const PCIDevice * d)207 static inline int pci_is_vf(const PCIDevice *d)
208 {
209 return d->exp.sriov_vf.pf != NULL;
210 }
211
pci_config_size(const PCIDevice * d)212 static inline uint32_t pci_config_size(const PCIDevice *d)
213 {
214 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
215 }
216
pci_get_bdf(PCIDevice * dev)217 static inline uint16_t pci_get_bdf(PCIDevice *dev)
218 {
219 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
220 }
221
222 uint16_t pci_requester_id(PCIDevice *dev);
223
224 /* DMA access functions */
pci_get_address_space(PCIDevice * dev)225 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
226 {
227 return &dev->bus_master_as;
228 }
229
230 /**
231 * pci_dma_rw: Read from or write to an address space from PCI device.
232 *
233 * Return a MemTxResult indicating whether the operation succeeded
234 * or failed (eg unassigned memory, device rejected the transaction,
235 * IOMMU fault).
236 *
237 * @dev: #PCIDevice doing the memory access
238 * @addr: address within the #PCIDevice address space
239 * @buf: buffer with the data transferred
240 * @len: the number of bytes to read or write
241 * @dir: indicates the transfer direction
242 */
pci_dma_rw(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len,DMADirection dir,MemTxAttrs attrs)243 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
244 void *buf, dma_addr_t len,
245 DMADirection dir, MemTxAttrs attrs)
246 {
247 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
248 dir, attrs);
249 }
250
251 /**
252 * pci_dma_read: Read from an address space from PCI device.
253 *
254 * Return a MemTxResult indicating whether the operation succeeded
255 * or failed (eg unassigned memory, device rejected the transaction,
256 * IOMMU fault). Called within RCU critical section.
257 *
258 * @dev: #PCIDevice doing the memory access
259 * @addr: address within the #PCIDevice address space
260 * @buf: buffer with the data transferred
261 * @len: length of the data transferred
262 */
pci_dma_read(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len)263 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
264 void *buf, dma_addr_t len)
265 {
266 return pci_dma_rw(dev, addr, buf, len,
267 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
268 }
269
270 /**
271 * pci_dma_write: Write to address space from PCI device.
272 *
273 * Return a MemTxResult indicating whether the operation succeeded
274 * or failed (eg unassigned memory, device rejected the transaction,
275 * IOMMU fault).
276 *
277 * @dev: #PCIDevice doing the memory access
278 * @addr: address within the #PCIDevice address space
279 * @buf: buffer with the data transferred
280 * @len: the number of bytes to write
281 */
pci_dma_write(PCIDevice * dev,dma_addr_t addr,const void * buf,dma_addr_t len)282 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
283 const void *buf, dma_addr_t len)
284 {
285 return pci_dma_rw(dev, addr, (void *) buf, len,
286 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
287 }
288
289 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
290 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
291 dma_addr_t addr, \
292 uint##_bits##_t *val, \
293 MemTxAttrs attrs) \
294 { \
295 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
296 } \
297 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
298 dma_addr_t addr, \
299 uint##_bits##_t val, \
300 MemTxAttrs attrs) \
301 { \
302 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
303 }
304
305 PCI_DMA_DEFINE_LDST(ub, b, 8);
306 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
307 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
308 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
309 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
310 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
311 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
312
313 #undef PCI_DMA_DEFINE_LDST
314
315 /**
316 * pci_dma_map: Map device PCI address space range into host virtual address
317 * @dev: #PCIDevice to be accessed
318 * @addr: address within that device's address space
319 * @plen: pointer to length of buffer; updated on return to indicate
320 * if only a subset of the requested range has been mapped
321 * @dir: indicates the transfer direction
322 *
323 * Return: A host pointer, or %NULL if the resources needed to
324 * perform the mapping are exhausted (in that case *@plen
325 * is set to zero).
326 */
pci_dma_map(PCIDevice * dev,dma_addr_t addr,dma_addr_t * plen,DMADirection dir)327 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
328 dma_addr_t *plen, DMADirection dir)
329 {
330 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
331 MEMTXATTRS_UNSPECIFIED);
332 }
333
pci_dma_unmap(PCIDevice * dev,void * buffer,dma_addr_t len,DMADirection dir,dma_addr_t access_len)334 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
335 DMADirection dir, dma_addr_t access_len)
336 {
337 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
338 }
339
pci_dma_sglist_init(QEMUSGList * qsg,PCIDevice * dev,int alloc_hint)340 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
341 int alloc_hint)
342 {
343 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
344 }
345
346 extern const VMStateDescription vmstate_pci_device;
347
348 #define VMSTATE_PCI_DEVICE(_field, _state) { \
349 .name = (stringify(_field)), \
350 .size = sizeof(PCIDevice), \
351 .vmsd = &vmstate_pci_device, \
352 .flags = VMS_STRUCT, \
353 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
354 }
355
356 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
357 .name = (stringify(_field)), \
358 .size = sizeof(PCIDevice), \
359 .vmsd = &vmstate_pci_device, \
360 .flags = VMS_STRUCT | VMS_POINTER, \
361 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
362 }
363
364 #endif
365