xref: /openbmc/qemu/include/hw/pci/pci_bus.h (revision f101c9fe)
1 #ifndef QEMU_PCI_BUS_H
2 #define QEMU_PCI_BUS_H
3 
4 #include "hw/pci/pci.h"
5 
6 /*
7  * PCI Bus datastructures.
8  *
9  * Do not access the following members directly;
10  * use accessor functions in pci.h
11  */
12 
13 struct PCIBusClass {
14     /*< private >*/
15     BusClass parent_class;
16     /*< public >*/
17 
18     int (*bus_num)(PCIBus *bus);
19     uint16_t (*numa_node)(PCIBus *bus);
20 };
21 
22 enum PCIBusFlags {
23     /* This bus is the root of a PCI domain */
24     PCI_BUS_IS_ROOT                                         = 0x0001,
25     /* PCIe extended configuration space is accessible on this bus */
26     PCI_BUS_EXTENDED_CONFIG_SPACE                           = 0x0002,
27 };
28 
29 struct PCIBus {
30     BusState qbus;
31     enum PCIBusFlags flags;
32     PCIIOMMUFunc iommu_fn;
33     void *iommu_opaque;
34     uint8_t devfn_min;
35     uint32_t slot_reserved_mask;
36     pci_set_irq_fn set_irq;
37     pci_map_irq_fn map_irq;
38     pci_route_irq_fn route_intx_to_irq;
39     void *irq_opaque;
40     PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
41     PCIDevice *parent_dev;
42     MemoryRegion *address_space_mem;
43     MemoryRegion *address_space_io;
44 
45     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
46     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
47 
48     /* The bus IRQ state is the logical OR of the connected devices.
49        Keep a count of the number of devices with raised IRQs.  */
50     int nirq;
51     int *irq_count;
52 
53     Notifier machine_done;
54 };
55 
56 static inline bool pci_bus_is_root(PCIBus *bus)
57 {
58     return !!(bus->flags & PCI_BUS_IS_ROOT);
59 }
60 
61 static inline bool pci_bus_allows_extended_config_space(PCIBus *bus)
62 {
63     return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE);
64 }
65 
66 #endif /* QEMU_PCI_BUS_H */
67