xref: /openbmc/qemu/include/hw/pci/pci_bus.h (revision 1fd6bb44)
1 #ifndef QEMU_PCI_BUS_H
2 #define QEMU_PCI_BUS_H
3 
4 /*
5  * PCI Bus and Bridge datastructures.
6  *
7  * Do not access the following members directly;
8  * use accessor functions in pci.h, pci_bridge.h
9  */
10 
11 struct PCIBus {
12     BusState qbus;
13     PCIDMAContextFunc dma_context_fn;
14     void *dma_context_opaque;
15     uint8_t devfn_min;
16     pci_set_irq_fn set_irq;
17     pci_map_irq_fn map_irq;
18     pci_route_irq_fn route_intx_to_irq;
19     pci_hotplug_fn hotplug;
20     DeviceState *hotplug_qdev;
21     void *irq_opaque;
22     PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
23     PCIDevice *parent_dev;
24     MemoryRegion *address_space_mem;
25     MemoryRegion *address_space_io;
26 
27     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
28     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
29 
30     /* The bus IRQ state is the logical OR of the connected devices.
31        Keep a count of the number of devices with raised IRQs.  */
32     int nirq;
33     int *irq_count;
34 };
35 
36 typedef struct PCIBridgeWindows PCIBridgeWindows;
37 
38 /*
39  * Aliases for each of the address space windows that the bridge
40  * can forward. Mapped into the bridge's parent's address space,
41  * as subregions.
42  */
43 struct PCIBridgeWindows {
44     MemoryRegion alias_pref_mem;
45     MemoryRegion alias_mem;
46     MemoryRegion alias_io;
47     /*
48      * When bridge control VGA forwarding is enabled, bridges will
49      * provide positive decode on the PCI VGA defined I/O port and
50      * MMIO ranges.  When enabled forwarding is only qualified on the
51      * I/O and memory enable bits in the bridge command register.
52      */
53     MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
54 };
55 
56 struct PCIBridge {
57     PCIDevice dev;
58 
59     /* private member */
60     PCIBus sec_bus;
61     /*
62      * Memory regions for the bridge's address spaces.  These regions are not
63      * directly added to system_memory/system_io or its descendants.
64      * Bridge's secondary bus points to these, so that devices
65      * under the bridge see these regions as its address spaces.
66      * The regions are as large as the entire address space -
67      * they don't take into account any windows.
68      */
69     MemoryRegion address_space_mem;
70     MemoryRegion address_space_io;
71 
72     PCIBridgeWindows *windows;
73 
74     pci_map_irq_fn map_irq;
75     const char *bus_name;
76 };
77 
78 #endif /* QEMU_PCI_BUS_H */
79