1 /* 2 * QEMU PCI bridge 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 19 * 20 * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc] 21 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 22 * VA Linux Systems Japan K.K. 23 * 24 */ 25 26 #ifndef QEMU_PCI_BRIDGE_H 27 #define QEMU_PCI_BRIDGE_H 28 29 #include "hw/pci/pci_device.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/cxl/cxl.h" 32 #include "qom/object.h" 33 34 typedef struct PCIBridgeWindows PCIBridgeWindows; 35 36 /* 37 * Aliases for each of the address space windows that the bridge 38 * can forward. Mapped into the bridge's parent's address space, 39 * as subregions. 40 */ 41 struct PCIBridgeWindows { 42 MemoryRegion alias_pref_mem; 43 MemoryRegion alias_mem; 44 MemoryRegion alias_io; 45 /* 46 * When bridge control VGA forwarding is enabled, bridges will 47 * provide positive decode on the PCI VGA defined I/O port and 48 * MMIO ranges. When enabled forwarding is only qualified on the 49 * I/O and memory enable bits in the bridge command register. 50 */ 51 MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; 52 }; 53 54 #define TYPE_PCI_BRIDGE "base-pci-bridge" 55 OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge, PCI_BRIDGE) 56 #define IS_PCI_BRIDGE(dev) object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE) 57 58 struct PCIBridge { 59 /*< private >*/ 60 PCIDevice parent_obj; 61 /*< public >*/ 62 63 /* private member */ 64 PCIBus sec_bus; 65 /* 66 * Memory regions for the bridge's address spaces. These regions are not 67 * directly added to system_memory/system_io or its descendants. 68 * Bridge's secondary bus points to these, so that devices 69 * under the bridge see these regions as its address spaces. 70 * The regions are as large as the entire address space - 71 * they don't take into account any windows. 72 */ 73 MemoryRegion address_space_mem; 74 MemoryRegion address_space_io; 75 AddressSpace as_mem; 76 AddressSpace as_io; 77 78 PCIBridgeWindows windows; 79 80 pci_map_irq_fn map_irq; 81 const char *bus_name; 82 83 /* SLT is RO for PCIE to PCIE bridges, but old QEMU versions had it RW */ 84 bool pcie_writeable_slt_bug; 85 }; 86 87 #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr" 88 #define PCI_BRIDGE_DEV_PROP_MSI "msi" 89 #define PCI_BRIDGE_DEV_PROP_SHPC "shpc" 90 typedef struct CXLHost CXLHost; 91 92 typedef struct PXBDev { 93 /*< private >*/ 94 PCIDevice parent_obj; 95 /*< public >*/ 96 97 uint8_t bus_nr; 98 uint16_t numa_node; 99 bool bypass_iommu; 100 } PXBDev; 101 102 typedef struct PXBPCIEDev { 103 /*< private >*/ 104 PXBDev parent_obj; 105 } PXBPCIEDev; 106 107 #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" 108 #define TYPE_PXB_DEV "pxb" 109 OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) 110 111 typedef struct PXBCXLDev { 112 /*< private >*/ 113 PXBPCIEDev parent_obj; 114 /*< public >*/ 115 116 bool hdm_for_passthrough; 117 CXLHost *cxl_host_bridge; /* Pointer to a CXLHost */ 118 } PXBCXLDev; 119 120 #define TYPE_PXB_CXL_DEV "pxb-cxl" 121 OBJECT_DECLARE_SIMPLE_TYPE(PXBCXLDev, PXB_CXL_DEV) 122 123 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 124 uint16_t svid, uint16_t ssid, 125 Error **errp); 126 127 PCIDevice *pci_bridge_get_device(PCIBus *bus); 128 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); 129 130 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type); 131 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); 132 133 void pci_bridge_update_mappings(PCIBridge *br); 134 void pci_bridge_write_config(PCIDevice *d, 135 uint32_t address, uint32_t val, int len); 136 void pci_bridge_disable_base_limit(PCIDevice *dev); 137 void pci_bridge_reset(DeviceState *qdev); 138 139 void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename); 140 void pci_bridge_exitfn(PCIDevice *pci_dev); 141 142 void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 143 Error **errp); 144 void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 145 Error **errp); 146 void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev, 147 DeviceState *dev, Error **errp); 148 149 /* 150 * before qdev initialization(qdev_init()), this function sets bus_name and 151 * map_irq callback which are necessary for pci_bridge_initfn() to 152 * initialize bus. 153 */ 154 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 155 pci_map_irq_fn map_irq); 156 157 /* TODO: add this define to pci_regs.h in linux and then in qemu. */ 158 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ 159 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ 160 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ 161 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ 162 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ 163 164 typedef struct PCIBridgeQemuCap { 165 uint8_t id; /* Standard PCI capability header field */ 166 uint8_t next; /* Standard PCI capability header field */ 167 uint8_t len; /* Standard PCI vendor-specific capability header field */ 168 uint8_t type; /* Red Hat vendor-specific capability type. 169 Types are defined with REDHAT_PCI_CAP_ prefix */ 170 171 uint32_t bus_res; /* Minimum number of buses to reserve */ 172 uint64_t io; /* IO space to reserve */ 173 uint32_t mem; /* Non-prefetchable memory to reserve */ 174 /* At most one of the following two fields may be set to a value 175 * different from -1 */ 176 uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */ 177 uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */ 178 } PCIBridgeQemuCap; 179 180 #define REDHAT_PCI_CAP_TYPE_OFFSET 3 181 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 182 183 /* 184 * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a 185 * capability in PCI configuration space to reserve on firmware init. 186 */ 187 typedef struct PCIResReserve { 188 uint32_t bus; 189 uint64_t io; 190 uint64_t mem_non_pref; 191 uint64_t mem_pref_32; 192 uint64_t mem_pref_64; 193 } PCIResReserve; 194 195 #define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4 196 #define REDHAT_PCI_CAP_RES_RESERVE_IO 8 197 #define REDHAT_PCI_CAP_RES_RESERVE_MEM 16 198 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20 199 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24 200 #define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32 201 202 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 203 PCIResReserve res_reserve, Error **errp); 204 205 #endif /* QEMU_PCI_BRIDGE_H */ 206