1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 #include "hw/pci/pcie.h" 11 #include "qom/object.h" 12 13 extern bool pci_available; 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 22 #define PCI_BUS_MAX 256 23 #define PCI_DEVFN_MAX 256 24 #define PCI_SLOT_MAX 32 25 #define PCI_FUNC_MAX 8 26 27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 28 #include "hw/pci/pci_ids.h" 29 30 /* QEMU-specific Vendor and Device ID definitions */ 31 32 /* IBM (0x1014) */ 33 #define PCI_DEVICE_ID_IBM_440GX 0x027f 34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 35 36 /* Hitachi (0x1054) */ 37 #define PCI_VENDOR_ID_HITACHI 0x1054 38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 39 40 /* Apple (0x106b) */ 41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 46 47 /* Realtek (0x10ec) */ 48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 49 50 /* Xilinx (0x10ee) */ 51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 52 53 /* Marvell (0x11ab) */ 54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 55 56 /* QEMU/Bochs VGA (0x1234) */ 57 #define PCI_VENDOR_ID_QEMU 0x1234 58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 59 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 60 61 /* VMWare (0x15ad) */ 62 #define PCI_VENDOR_ID_VMWARE 0x15ad 63 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 64 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 65 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 66 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 67 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 68 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 69 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 70 71 /* Intel (0x8086) */ 72 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 73 #define PCI_DEVICE_ID_INTEL_82557 0x1229 74 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 75 76 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 77 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 79 #define PCI_SUBDEVICE_ID_QEMU 0x1100 80 81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 89 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013 90 #define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014 91 #define PCI_DEVICE_ID_VIRTIO_MEM 0x1015 92 93 #define PCI_VENDOR_ID_REDHAT 0x1b36 94 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 95 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 96 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 97 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 98 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 99 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 100 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 101 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 102 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 103 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 104 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 105 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 106 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 107 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 108 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 109 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 110 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 111 112 #define FMT_PCIBUS PRIx64 113 114 typedef uint64_t pcibus_t; 115 116 struct PCIHostDeviceAddress { 117 unsigned int domain; 118 unsigned int bus; 119 unsigned int slot; 120 unsigned int function; 121 }; 122 123 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 124 uint32_t address, uint32_t data, int len); 125 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 126 uint32_t address, int len); 127 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 128 pcibus_t addr, pcibus_t size, int type); 129 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 130 131 typedef struct PCIIORegion { 132 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 133 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 134 pcibus_t size; 135 uint8_t type; 136 MemoryRegion *memory; 137 MemoryRegion *address_space; 138 } PCIIORegion; 139 140 #define PCI_ROM_SLOT 6 141 #define PCI_NUM_REGIONS 7 142 143 enum { 144 QEMU_PCI_VGA_MEM, 145 QEMU_PCI_VGA_IO_LO, 146 QEMU_PCI_VGA_IO_HI, 147 QEMU_PCI_VGA_NUM_REGIONS, 148 }; 149 150 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 151 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 152 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 153 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 154 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 155 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 156 157 #include "hw/pci/pci_regs.h" 158 159 /* PCI HEADER_TYPE */ 160 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 161 162 /* Size of the standard PCI config header */ 163 #define PCI_CONFIG_HEADER_SIZE 0x40 164 /* Size of the standard PCI config space */ 165 #define PCI_CONFIG_SPACE_SIZE 0x100 166 /* Size of the standard PCIe config space: 4KB */ 167 #define PCIE_CONFIG_SPACE_SIZE 0x1000 168 169 #define PCI_NUM_PINS 4 /* A-D */ 170 171 /* Bits in cap_present field. */ 172 enum { 173 QEMU_PCI_CAP_MSI = 0x1, 174 QEMU_PCI_CAP_MSIX = 0x2, 175 QEMU_PCI_CAP_EXPRESS = 0x4, 176 177 /* multifunction capable device */ 178 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 179 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 180 181 /* command register SERR bit enabled - unused since QEMU v5.0 */ 182 #define QEMU_PCI_CAP_SERR_BITNR 4 183 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 184 /* Standard hot plug controller. */ 185 #define QEMU_PCI_SHPC_BITNR 5 186 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 187 #define QEMU_PCI_SLOTID_BITNR 6 188 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 189 /* PCI Express capability - Power Controller Present */ 190 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 191 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 192 /* Link active status in endpoint capability is always set */ 193 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 194 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 195 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 196 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 197 }; 198 199 #define TYPE_PCI_DEVICE "pci-device" 200 typedef struct PCIDeviceClass PCIDeviceClass; 201 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 202 PCI_DEVICE, TYPE_PCI_DEVICE) 203 204 /* Implemented by devices that can be plugged on PCI Express buses */ 205 #define INTERFACE_PCIE_DEVICE "pci-express-device" 206 207 /* Implemented by devices that can be plugged on Conventional PCI buses */ 208 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 209 210 typedef struct PCIINTxRoute { 211 enum { 212 PCI_INTX_ENABLED, 213 PCI_INTX_INVERTED, 214 PCI_INTX_DISABLED, 215 } mode; 216 int irq; 217 } PCIINTxRoute; 218 219 struct PCIDeviceClass { 220 DeviceClass parent_class; 221 222 void (*realize)(PCIDevice *dev, Error **errp); 223 PCIUnregisterFunc *exit; 224 PCIConfigReadFunc *config_read; 225 PCIConfigWriteFunc *config_write; 226 227 uint16_t vendor_id; 228 uint16_t device_id; 229 uint8_t revision; 230 uint16_t class_id; 231 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 232 uint16_t subsystem_id; /* only for header type = 0 */ 233 234 /* 235 * pci-to-pci bridge or normal device. 236 * This doesn't mean pci host switch. 237 * When card bus bridge is supported, this would be enhanced. 238 */ 239 bool is_bridge; 240 241 /* rom bar */ 242 const char *romfile; 243 }; 244 245 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 246 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 247 MSIMessage msg); 248 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 249 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 250 unsigned int vector_start, 251 unsigned int vector_end); 252 253 enum PCIReqIDType { 254 PCI_REQ_ID_INVALID = 0, 255 PCI_REQ_ID_BDF, 256 PCI_REQ_ID_SECONDARY_BUS, 257 PCI_REQ_ID_MAX, 258 }; 259 typedef enum PCIReqIDType PCIReqIDType; 260 261 struct PCIReqIDCache { 262 PCIDevice *dev; 263 PCIReqIDType type; 264 }; 265 typedef struct PCIReqIDCache PCIReqIDCache; 266 267 struct PCIDevice { 268 DeviceState qdev; 269 bool partially_hotplugged; 270 271 /* PCI config space */ 272 uint8_t *config; 273 274 /* Used to enable config checks on load. Note that writable bits are 275 * never checked even if set in cmask. */ 276 uint8_t *cmask; 277 278 /* Used to implement R/W bytes */ 279 uint8_t *wmask; 280 281 /* Used to implement RW1C(Write 1 to Clear) bytes */ 282 uint8_t *w1cmask; 283 284 /* Used to allocate config space for capabilities. */ 285 uint8_t *used; 286 287 /* the following fields are read only */ 288 int32_t devfn; 289 /* Cached device to fetch requester ID from, to avoid the PCI 290 * tree walking every time we invoke PCI request (e.g., 291 * MSI). For conventional PCI root complex, this field is 292 * meaningless. */ 293 PCIReqIDCache requester_id_cache; 294 char name[64]; 295 PCIIORegion io_regions[PCI_NUM_REGIONS]; 296 AddressSpace bus_master_as; 297 MemoryRegion bus_master_container_region; 298 MemoryRegion bus_master_enable_region; 299 300 /* do not access the following fields */ 301 PCIConfigReadFunc *config_read; 302 PCIConfigWriteFunc *config_write; 303 304 /* Legacy PCI VGA regions */ 305 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 306 bool has_vga; 307 308 /* Current IRQ levels. Used internally by the generic PCI code. */ 309 uint8_t irq_state; 310 311 /* Capability bits */ 312 uint32_t cap_present; 313 314 /* Offset of MSI-X capability in config space */ 315 uint8_t msix_cap; 316 317 /* MSI-X entries */ 318 int msix_entries_nr; 319 320 /* Space to store MSIX table & pending bit array */ 321 uint8_t *msix_table; 322 uint8_t *msix_pba; 323 /* MemoryRegion container for msix exclusive BAR setup */ 324 MemoryRegion msix_exclusive_bar; 325 /* Memory Regions for MSIX table and pending bit entries. */ 326 MemoryRegion msix_table_mmio; 327 MemoryRegion msix_pba_mmio; 328 /* Reference-count for entries actually in use by driver. */ 329 unsigned *msix_entry_used; 330 /* MSIX function mask set or MSIX disabled */ 331 bool msix_function_masked; 332 /* Version id needed for VMState */ 333 int32_t version_id; 334 335 /* Offset of MSI capability in config space */ 336 uint8_t msi_cap; 337 338 /* PCI Express */ 339 PCIExpressDevice exp; 340 341 /* SHPC */ 342 SHPCDevice *shpc; 343 344 /* Location of option rom */ 345 char *romfile; 346 bool has_rom; 347 MemoryRegion rom; 348 uint32_t rom_bar; 349 350 /* INTx routing notifier */ 351 PCIINTxRoutingNotifier intx_routing_notifier; 352 353 /* MSI-X notifiers */ 354 MSIVectorUseNotifier msix_vector_use_notifier; 355 MSIVectorReleaseNotifier msix_vector_release_notifier; 356 MSIVectorPollNotifier msix_vector_poll_notifier; 357 358 /* ID of standby device in net_failover pair */ 359 char *failover_pair_id; 360 }; 361 362 void pci_register_bar(PCIDevice *pci_dev, int region_num, 363 uint8_t attr, MemoryRegion *memory); 364 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 365 MemoryRegion *io_lo, MemoryRegion *io_hi); 366 void pci_unregister_vga(PCIDevice *pci_dev); 367 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 368 369 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 370 uint8_t offset, uint8_t size, 371 Error **errp); 372 373 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 374 375 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 376 377 378 uint32_t pci_default_read_config(PCIDevice *d, 379 uint32_t address, int len); 380 void pci_default_write_config(PCIDevice *d, 381 uint32_t address, uint32_t val, int len); 382 void pci_device_save(PCIDevice *s, QEMUFile *f); 383 int pci_device_load(PCIDevice *s, QEMUFile *f); 384 MemoryRegion *pci_address_space(PCIDevice *dev); 385 MemoryRegion *pci_address_space_io(PCIDevice *dev); 386 387 /* 388 * Should not normally be used by devices. For use by sPAPR target 389 * where QEMU emulates firmware. 390 */ 391 int pci_bar(PCIDevice *d, int reg); 392 393 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 394 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 395 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 396 397 #define TYPE_PCI_BUS "PCI" 398 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 399 #define TYPE_PCIE_BUS "PCIE" 400 401 bool pci_bus_is_express(PCIBus *bus); 402 403 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 404 const char *name, 405 MemoryRegion *address_space_mem, 406 MemoryRegion *address_space_io, 407 uint8_t devfn_min, const char *typename); 408 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 409 MemoryRegion *address_space_mem, 410 MemoryRegion *address_space_io, 411 uint8_t devfn_min, const char *typename); 412 void pci_root_bus_cleanup(PCIBus *bus); 413 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 414 void *irq_opaque, int nirq); 415 void pci_bus_irqs_cleanup(PCIBus *bus); 416 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 417 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 418 static inline int pci_swizzle(int slot, int pin) 419 { 420 return (slot + pin) % PCI_NUM_PINS; 421 } 422 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 423 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 424 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 425 void *irq_opaque, 426 MemoryRegion *address_space_mem, 427 MemoryRegion *address_space_io, 428 uint8_t devfn_min, int nirq, 429 const char *typename); 430 void pci_unregister_root_bus(PCIBus *bus); 431 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 432 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 433 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 434 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 435 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 436 PCIINTxRoutingNotifier notifier); 437 void pci_device_reset(PCIDevice *dev); 438 439 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 440 const char *default_model, 441 const char *default_devaddr); 442 443 PCIDevice *pci_vga_init(PCIBus *bus); 444 445 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 446 { 447 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 448 } 449 int pci_bus_num(PCIBus *s); 450 static inline int pci_dev_bus_num(const PCIDevice *dev) 451 { 452 return pci_bus_num(pci_get_bus(dev)); 453 } 454 455 int pci_bus_numa_node(PCIBus *bus); 456 void pci_for_each_device(PCIBus *bus, int bus_num, 457 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 458 void *opaque); 459 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 460 void (*fn)(PCIBus *bus, PCIDevice *d, 461 void *opaque), 462 void *opaque); 463 void pci_for_each_bus_depth_first(PCIBus *bus, 464 void *(*begin)(PCIBus *bus, void *parent_state), 465 void (*end)(PCIBus *bus, void *state), 466 void *parent_state); 467 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 468 469 /* Use this wrapper when specific scan order is not required. */ 470 static inline 471 void pci_for_each_bus(PCIBus *bus, 472 void (*fn)(PCIBus *bus, void *opaque), 473 void *opaque) 474 { 475 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 476 } 477 478 PCIBus *pci_device_root_bus(const PCIDevice *d); 479 const char *pci_root_bus_path(PCIDevice *dev); 480 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 481 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 482 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 483 484 void pci_device_deassert_intx(PCIDevice *dev); 485 486 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 487 488 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 489 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 490 491 static inline void 492 pci_set_byte(uint8_t *config, uint8_t val) 493 { 494 *config = val; 495 } 496 497 static inline uint8_t 498 pci_get_byte(const uint8_t *config) 499 { 500 return *config; 501 } 502 503 static inline void 504 pci_set_word(uint8_t *config, uint16_t val) 505 { 506 stw_le_p(config, val); 507 } 508 509 static inline uint16_t 510 pci_get_word(const uint8_t *config) 511 { 512 return lduw_le_p(config); 513 } 514 515 static inline void 516 pci_set_long(uint8_t *config, uint32_t val) 517 { 518 stl_le_p(config, val); 519 } 520 521 static inline uint32_t 522 pci_get_long(const uint8_t *config) 523 { 524 return ldl_le_p(config); 525 } 526 527 /* 528 * PCI capabilities and/or their fields 529 * are generally DWORD aligned only so 530 * mechanism used by pci_set/get_quad() 531 * must be tolerant to unaligned pointers 532 * 533 */ 534 static inline void 535 pci_set_quad(uint8_t *config, uint64_t val) 536 { 537 stq_le_p(config, val); 538 } 539 540 static inline uint64_t 541 pci_get_quad(const uint8_t *config) 542 { 543 return ldq_le_p(config); 544 } 545 546 static inline void 547 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 548 { 549 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 550 } 551 552 static inline void 553 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 554 { 555 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 556 } 557 558 static inline void 559 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 560 { 561 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 562 } 563 564 static inline void 565 pci_config_set_class(uint8_t *pci_config, uint16_t val) 566 { 567 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 568 } 569 570 static inline void 571 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 572 { 573 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 574 } 575 576 static inline void 577 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 578 { 579 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 580 } 581 582 /* 583 * helper functions to do bit mask operation on configuration space. 584 * Just to set bit, use test-and-set and discard returned value. 585 * Just to clear bit, use test-and-clear and discard returned value. 586 * NOTE: They aren't atomic. 587 */ 588 static inline uint8_t 589 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 590 { 591 uint8_t val = pci_get_byte(config); 592 pci_set_byte(config, val & ~mask); 593 return val & mask; 594 } 595 596 static inline uint8_t 597 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 598 { 599 uint8_t val = pci_get_byte(config); 600 pci_set_byte(config, val | mask); 601 return val & mask; 602 } 603 604 static inline uint16_t 605 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 606 { 607 uint16_t val = pci_get_word(config); 608 pci_set_word(config, val & ~mask); 609 return val & mask; 610 } 611 612 static inline uint16_t 613 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 614 { 615 uint16_t val = pci_get_word(config); 616 pci_set_word(config, val | mask); 617 return val & mask; 618 } 619 620 static inline uint32_t 621 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 622 { 623 uint32_t val = pci_get_long(config); 624 pci_set_long(config, val & ~mask); 625 return val & mask; 626 } 627 628 static inline uint32_t 629 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 630 { 631 uint32_t val = pci_get_long(config); 632 pci_set_long(config, val | mask); 633 return val & mask; 634 } 635 636 static inline uint64_t 637 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 638 { 639 uint64_t val = pci_get_quad(config); 640 pci_set_quad(config, val & ~mask); 641 return val & mask; 642 } 643 644 static inline uint64_t 645 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 646 { 647 uint64_t val = pci_get_quad(config); 648 pci_set_quad(config, val | mask); 649 return val & mask; 650 } 651 652 /* Access a register specified by a mask */ 653 static inline void 654 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 655 { 656 uint8_t val = pci_get_byte(config); 657 uint8_t rval = reg << ctz32(mask); 658 pci_set_byte(config, (~mask & val) | (mask & rval)); 659 } 660 661 static inline uint8_t 662 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 663 { 664 uint8_t val = pci_get_byte(config); 665 return (val & mask) >> ctz32(mask); 666 } 667 668 static inline void 669 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 670 { 671 uint16_t val = pci_get_word(config); 672 uint16_t rval = reg << ctz32(mask); 673 pci_set_word(config, (~mask & val) | (mask & rval)); 674 } 675 676 static inline uint16_t 677 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 678 { 679 uint16_t val = pci_get_word(config); 680 return (val & mask) >> ctz32(mask); 681 } 682 683 static inline void 684 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 685 { 686 uint32_t val = pci_get_long(config); 687 uint32_t rval = reg << ctz32(mask); 688 pci_set_long(config, (~mask & val) | (mask & rval)); 689 } 690 691 static inline uint32_t 692 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 693 { 694 uint32_t val = pci_get_long(config); 695 return (val & mask) >> ctz32(mask); 696 } 697 698 static inline void 699 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 700 { 701 uint64_t val = pci_get_quad(config); 702 uint64_t rval = reg << ctz32(mask); 703 pci_set_quad(config, (~mask & val) | (mask & rval)); 704 } 705 706 static inline uint64_t 707 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 708 { 709 uint64_t val = pci_get_quad(config); 710 return (val & mask) >> ctz32(mask); 711 } 712 713 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 714 const char *name); 715 PCIDevice *pci_new(int devfn, const char *name); 716 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 717 718 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 719 bool multifunction, 720 const char *name); 721 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 722 723 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 724 725 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 726 void pci_set_irq(PCIDevice *pci_dev, int level); 727 728 static inline void pci_irq_assert(PCIDevice *pci_dev) 729 { 730 pci_set_irq(pci_dev, 1); 731 } 732 733 static inline void pci_irq_deassert(PCIDevice *pci_dev) 734 { 735 pci_set_irq(pci_dev, 0); 736 } 737 738 /* 739 * FIXME: PCI does not work this way. 740 * All the callers to this method should be fixed. 741 */ 742 static inline void pci_irq_pulse(PCIDevice *pci_dev) 743 { 744 pci_irq_assert(pci_dev); 745 pci_irq_deassert(pci_dev); 746 } 747 748 static inline int pci_is_express(const PCIDevice *d) 749 { 750 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 751 } 752 753 static inline int pci_is_express_downstream_port(const PCIDevice *d) 754 { 755 uint8_t type; 756 757 if (!pci_is_express(d) || !d->exp.exp_cap) { 758 return 0; 759 } 760 761 type = pcie_cap_get_type(d); 762 763 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 764 } 765 766 static inline uint32_t pci_config_size(const PCIDevice *d) 767 { 768 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 769 } 770 771 static inline uint16_t pci_get_bdf(PCIDevice *dev) 772 { 773 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 774 } 775 776 uint16_t pci_requester_id(PCIDevice *dev); 777 778 /* DMA access functions */ 779 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 780 { 781 return &dev->bus_master_as; 782 } 783 784 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 785 void *buf, dma_addr_t len, DMADirection dir) 786 { 787 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 788 } 789 790 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 791 void *buf, dma_addr_t len) 792 { 793 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 794 } 795 796 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 797 const void *buf, dma_addr_t len) 798 { 799 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 800 } 801 802 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 803 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 804 dma_addr_t addr) \ 805 { \ 806 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 807 } \ 808 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 809 dma_addr_t addr, uint##_bits##_t val) \ 810 { \ 811 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 812 } 813 814 PCI_DMA_DEFINE_LDST(ub, b, 8); 815 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 816 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 817 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 818 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 819 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 820 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 821 822 #undef PCI_DMA_DEFINE_LDST 823 824 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 825 dma_addr_t *plen, DMADirection dir) 826 { 827 void *buf; 828 829 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 830 return buf; 831 } 832 833 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 834 DMADirection dir, dma_addr_t access_len) 835 { 836 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 837 } 838 839 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 840 int alloc_hint) 841 { 842 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 843 } 844 845 extern const VMStateDescription vmstate_pci_device; 846 847 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 848 .name = (stringify(_field)), \ 849 .size = sizeof(PCIDevice), \ 850 .vmsd = &vmstate_pci_device, \ 851 .flags = VMS_STRUCT, \ 852 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 853 } 854 855 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 856 .name = (stringify(_field)), \ 857 .size = sizeof(PCIDevice), \ 858 .vmsd = &vmstate_pci_device, \ 859 .flags = VMS_STRUCT|VMS_POINTER, \ 860 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 861 } 862 863 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 864 865 #endif 866