1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 58 59 /* VMWare (0x15ad) */ 60 #define PCI_VENDOR_ID_VMWARE 0x15ad 61 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 62 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 63 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 64 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 65 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 66 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 67 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 68 69 /* Intel (0x8086) */ 70 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 71 #define PCI_DEVICE_ID_INTEL_82557 0x1229 72 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 73 74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBDEVICE_ID_QEMU 0x1100 78 79 /* legacy virtio-pci devices */ 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 /* 90 * modern virtio-pci devices get their id assigned automatically, 91 * there is no need to add #defines here. It gets calculated as 92 * 93 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 94 * virtio_bus_get_vdev_id(bus) 95 */ 96 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 97 98 #define PCI_VENDOR_ID_REDHAT 0x1b36 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 100 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 101 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 102 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 103 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 104 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 105 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 106 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 107 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 108 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 109 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 110 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 111 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 112 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 113 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 114 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 115 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 116 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 117 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 118 119 #define FMT_PCIBUS PRIx64 120 121 typedef uint64_t pcibus_t; 122 123 struct PCIHostDeviceAddress { 124 unsigned int domain; 125 unsigned int bus; 126 unsigned int slot; 127 unsigned int function; 128 }; 129 130 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 131 uint32_t address, uint32_t data, int len); 132 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 133 uint32_t address, int len); 134 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 135 pcibus_t addr, pcibus_t size, int type); 136 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 137 138 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 139 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 140 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 141 142 typedef struct PCIIORegion { 143 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 144 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 145 pcibus_t size; 146 uint8_t type; 147 MemoryRegion *memory; 148 MemoryRegion *address_space; 149 } PCIIORegion; 150 151 #define PCI_ROM_SLOT 6 152 #define PCI_NUM_REGIONS 7 153 154 enum { 155 QEMU_PCI_VGA_MEM, 156 QEMU_PCI_VGA_IO_LO, 157 QEMU_PCI_VGA_IO_HI, 158 QEMU_PCI_VGA_NUM_REGIONS, 159 }; 160 161 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 162 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 163 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 164 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 165 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 166 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 167 168 #include "hw/pci/pci_regs.h" 169 #include "hw/pci/pcie.h" 170 171 /* PCI HEADER_TYPE */ 172 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 173 174 /* Size of the standard PCI config header */ 175 #define PCI_CONFIG_HEADER_SIZE 0x40 176 /* Size of the standard PCI config space */ 177 #define PCI_CONFIG_SPACE_SIZE 0x100 178 /* Size of the standard PCIe config space: 4KB */ 179 #define PCIE_CONFIG_SPACE_SIZE 0x1000 180 181 #define PCI_NUM_PINS 4 /* A-D */ 182 183 /* Bits in cap_present field. */ 184 enum { 185 QEMU_PCI_CAP_MSI = 0x1, 186 QEMU_PCI_CAP_MSIX = 0x2, 187 QEMU_PCI_CAP_EXPRESS = 0x4, 188 189 /* multifunction capable device */ 190 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 191 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 192 193 /* command register SERR bit enabled - unused since QEMU v5.0 */ 194 #define QEMU_PCI_CAP_SERR_BITNR 4 195 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 196 /* Standard hot plug controller. */ 197 #define QEMU_PCI_SHPC_BITNR 5 198 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 199 #define QEMU_PCI_SLOTID_BITNR 6 200 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 201 /* PCI Express capability - Power Controller Present */ 202 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 203 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 204 /* Link active status in endpoint capability is always set */ 205 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 206 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 207 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 208 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 209 #define QEMU_PCIE_CXL_BITNR 10 210 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 211 }; 212 213 #define TYPE_PCI_DEVICE "pci-device" 214 typedef struct PCIDeviceClass PCIDeviceClass; 215 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 216 PCI_DEVICE, TYPE_PCI_DEVICE) 217 218 /* 219 * Implemented by devices that can be plugged on CXL buses. In the spec, this is 220 * actually a "CXL Component, but we name it device to match the PCI naming. 221 */ 222 #define INTERFACE_CXL_DEVICE "cxl-device" 223 224 /* Implemented by devices that can be plugged on PCI Express buses */ 225 #define INTERFACE_PCIE_DEVICE "pci-express-device" 226 227 /* Implemented by devices that can be plugged on Conventional PCI buses */ 228 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 229 230 typedef struct PCIINTxRoute { 231 enum { 232 PCI_INTX_ENABLED, 233 PCI_INTX_INVERTED, 234 PCI_INTX_DISABLED, 235 } mode; 236 int irq; 237 } PCIINTxRoute; 238 239 struct PCIDeviceClass { 240 DeviceClass parent_class; 241 242 void (*realize)(PCIDevice *dev, Error **errp); 243 PCIUnregisterFunc *exit; 244 PCIConfigReadFunc *config_read; 245 PCIConfigWriteFunc *config_write; 246 247 uint16_t vendor_id; 248 uint16_t device_id; 249 uint8_t revision; 250 uint16_t class_id; 251 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 252 uint16_t subsystem_id; /* only for header type = 0 */ 253 254 const char *romfile; /* rom bar */ 255 }; 256 257 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 258 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 259 MSIMessage msg); 260 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 261 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 262 unsigned int vector_start, 263 unsigned int vector_end); 264 265 enum PCIReqIDType { 266 PCI_REQ_ID_INVALID = 0, 267 PCI_REQ_ID_BDF, 268 PCI_REQ_ID_SECONDARY_BUS, 269 PCI_REQ_ID_MAX, 270 }; 271 typedef enum PCIReqIDType PCIReqIDType; 272 273 struct PCIReqIDCache { 274 PCIDevice *dev; 275 PCIReqIDType type; 276 }; 277 typedef struct PCIReqIDCache PCIReqIDCache; 278 279 struct PCIDevice { 280 DeviceState qdev; 281 bool partially_hotplugged; 282 bool has_power; 283 284 /* PCI config space */ 285 uint8_t *config; 286 287 /* Used to enable config checks on load. Note that writable bits are 288 * never checked even if set in cmask. */ 289 uint8_t *cmask; 290 291 /* Used to implement R/W bytes */ 292 uint8_t *wmask; 293 294 /* Used to implement RW1C(Write 1 to Clear) bytes */ 295 uint8_t *w1cmask; 296 297 /* Used to allocate config space for capabilities. */ 298 uint8_t *used; 299 300 /* the following fields are read only */ 301 int32_t devfn; 302 /* Cached device to fetch requester ID from, to avoid the PCI 303 * tree walking every time we invoke PCI request (e.g., 304 * MSI). For conventional PCI root complex, this field is 305 * meaningless. */ 306 PCIReqIDCache requester_id_cache; 307 char name[64]; 308 PCIIORegion io_regions[PCI_NUM_REGIONS]; 309 AddressSpace bus_master_as; 310 MemoryRegion bus_master_container_region; 311 MemoryRegion bus_master_enable_region; 312 313 /* do not access the following fields */ 314 PCIConfigReadFunc *config_read; 315 PCIConfigWriteFunc *config_write; 316 317 /* Legacy PCI VGA regions */ 318 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 319 bool has_vga; 320 321 /* Current IRQ levels. Used internally by the generic PCI code. */ 322 uint8_t irq_state; 323 324 /* Capability bits */ 325 uint32_t cap_present; 326 327 /* Offset of MSI-X capability in config space */ 328 uint8_t msix_cap; 329 330 /* MSI-X entries */ 331 int msix_entries_nr; 332 333 /* Space to store MSIX table & pending bit array */ 334 uint8_t *msix_table; 335 uint8_t *msix_pba; 336 337 /* May be used by INTx or MSI during interrupt notification */ 338 void *irq_opaque; 339 340 MSITriggerFunc *msi_trigger; 341 MSIPrepareMessageFunc *msi_prepare_message; 342 MSIxPrepareMessageFunc *msix_prepare_message; 343 344 /* MemoryRegion container for msix exclusive BAR setup */ 345 MemoryRegion msix_exclusive_bar; 346 /* Memory Regions for MSIX table and pending bit entries. */ 347 MemoryRegion msix_table_mmio; 348 MemoryRegion msix_pba_mmio; 349 /* Reference-count for entries actually in use by driver. */ 350 unsigned *msix_entry_used; 351 /* MSIX function mask set or MSIX disabled */ 352 bool msix_function_masked; 353 /* Version id needed for VMState */ 354 int32_t version_id; 355 356 /* Offset of MSI capability in config space */ 357 uint8_t msi_cap; 358 359 /* PCI Express */ 360 PCIExpressDevice exp; 361 362 /* SHPC */ 363 SHPCDevice *shpc; 364 365 /* Location of option rom */ 366 char *romfile; 367 uint32_t romsize; 368 bool has_rom; 369 MemoryRegion rom; 370 uint32_t rom_bar; 371 372 /* INTx routing notifier */ 373 PCIINTxRoutingNotifier intx_routing_notifier; 374 375 /* MSI-X notifiers */ 376 MSIVectorUseNotifier msix_vector_use_notifier; 377 MSIVectorReleaseNotifier msix_vector_release_notifier; 378 MSIVectorPollNotifier msix_vector_poll_notifier; 379 380 /* ID of standby device in net_failover pair */ 381 char *failover_pair_id; 382 uint32_t acpi_index; 383 }; 384 385 void pci_register_bar(PCIDevice *pci_dev, int region_num, 386 uint8_t attr, MemoryRegion *memory); 387 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 388 MemoryRegion *io_lo, MemoryRegion *io_hi); 389 void pci_unregister_vga(PCIDevice *pci_dev); 390 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 391 392 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 393 uint8_t offset, uint8_t size, 394 Error **errp); 395 396 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 397 398 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 399 400 401 uint32_t pci_default_read_config(PCIDevice *d, 402 uint32_t address, int len); 403 void pci_default_write_config(PCIDevice *d, 404 uint32_t address, uint32_t val, int len); 405 void pci_device_save(PCIDevice *s, QEMUFile *f); 406 int pci_device_load(PCIDevice *s, QEMUFile *f); 407 MemoryRegion *pci_address_space(PCIDevice *dev); 408 MemoryRegion *pci_address_space_io(PCIDevice *dev); 409 410 /* 411 * Should not normally be used by devices. For use by sPAPR target 412 * where QEMU emulates firmware. 413 */ 414 int pci_bar(PCIDevice *d, int reg); 415 416 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 417 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 418 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 419 420 #define TYPE_PCI_BUS "PCI" 421 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 422 #define TYPE_PCIE_BUS "PCIE" 423 #define TYPE_CXL_BUS "CXL" 424 425 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 426 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 427 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 428 429 bool pci_bus_is_express(PCIBus *bus); 430 431 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 432 const char *name, 433 MemoryRegion *address_space_mem, 434 MemoryRegion *address_space_io, 435 uint8_t devfn_min, const char *typename); 436 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 437 MemoryRegion *address_space_mem, 438 MemoryRegion *address_space_io, 439 uint8_t devfn_min, const char *typename); 440 void pci_root_bus_cleanup(PCIBus *bus); 441 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 442 void *irq_opaque, int nirq); 443 void pci_bus_irqs_cleanup(PCIBus *bus); 444 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 445 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 446 static inline int pci_swizzle(int slot, int pin) 447 { 448 return (slot + pin) % PCI_NUM_PINS; 449 } 450 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 451 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 452 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 453 void *irq_opaque, 454 MemoryRegion *address_space_mem, 455 MemoryRegion *address_space_io, 456 uint8_t devfn_min, int nirq, 457 const char *typename); 458 void pci_unregister_root_bus(PCIBus *bus); 459 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 460 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 461 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 462 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 463 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 464 PCIINTxRoutingNotifier notifier); 465 void pci_device_reset(PCIDevice *dev); 466 467 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 468 const char *default_model, 469 const char *default_devaddr); 470 471 PCIDevice *pci_vga_init(PCIBus *bus); 472 473 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 474 { 475 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 476 } 477 int pci_bus_num(PCIBus *s); 478 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 479 static inline int pci_dev_bus_num(const PCIDevice *dev) 480 { 481 return pci_bus_num(pci_get_bus(dev)); 482 } 483 484 int pci_bus_numa_node(PCIBus *bus); 485 void pci_for_each_device(PCIBus *bus, int bus_num, 486 pci_bus_dev_fn fn, 487 void *opaque); 488 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 489 pci_bus_dev_fn fn, 490 void *opaque); 491 void pci_for_each_device_under_bus(PCIBus *bus, 492 pci_bus_dev_fn fn, void *opaque); 493 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 494 pci_bus_dev_fn fn, 495 void *opaque); 496 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 497 pci_bus_fn end, void *parent_state); 498 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 499 500 /* Use this wrapper when specific scan order is not required. */ 501 static inline 502 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 503 { 504 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 505 } 506 507 PCIBus *pci_device_root_bus(const PCIDevice *d); 508 const char *pci_root_bus_path(PCIDevice *dev); 509 bool pci_bus_bypass_iommu(PCIBus *bus); 510 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 511 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 512 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 513 514 void pci_device_deassert_intx(PCIDevice *dev); 515 516 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 517 518 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 519 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 520 521 pcibus_t pci_bar_address(PCIDevice *d, 522 int reg, uint8_t type, pcibus_t size); 523 524 static inline void 525 pci_set_byte(uint8_t *config, uint8_t val) 526 { 527 *config = val; 528 } 529 530 static inline uint8_t 531 pci_get_byte(const uint8_t *config) 532 { 533 return *config; 534 } 535 536 static inline void 537 pci_set_word(uint8_t *config, uint16_t val) 538 { 539 stw_le_p(config, val); 540 } 541 542 static inline uint16_t 543 pci_get_word(const uint8_t *config) 544 { 545 return lduw_le_p(config); 546 } 547 548 static inline void 549 pci_set_long(uint8_t *config, uint32_t val) 550 { 551 stl_le_p(config, val); 552 } 553 554 static inline uint32_t 555 pci_get_long(const uint8_t *config) 556 { 557 return ldl_le_p(config); 558 } 559 560 /* 561 * PCI capabilities and/or their fields 562 * are generally DWORD aligned only so 563 * mechanism used by pci_set/get_quad() 564 * must be tolerant to unaligned pointers 565 * 566 */ 567 static inline void 568 pci_set_quad(uint8_t *config, uint64_t val) 569 { 570 stq_le_p(config, val); 571 } 572 573 static inline uint64_t 574 pci_get_quad(const uint8_t *config) 575 { 576 return ldq_le_p(config); 577 } 578 579 static inline void 580 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 581 { 582 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 583 } 584 585 static inline void 586 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 587 { 588 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 589 } 590 591 static inline void 592 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 593 { 594 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 595 } 596 597 static inline void 598 pci_config_set_class(uint8_t *pci_config, uint16_t val) 599 { 600 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 601 } 602 603 static inline void 604 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 605 { 606 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 607 } 608 609 static inline void 610 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 611 { 612 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 613 } 614 615 /* 616 * helper functions to do bit mask operation on configuration space. 617 * Just to set bit, use test-and-set and discard returned value. 618 * Just to clear bit, use test-and-clear and discard returned value. 619 * NOTE: They aren't atomic. 620 */ 621 static inline uint8_t 622 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 623 { 624 uint8_t val = pci_get_byte(config); 625 pci_set_byte(config, val & ~mask); 626 return val & mask; 627 } 628 629 static inline uint8_t 630 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 631 { 632 uint8_t val = pci_get_byte(config); 633 pci_set_byte(config, val | mask); 634 return val & mask; 635 } 636 637 static inline uint16_t 638 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 639 { 640 uint16_t val = pci_get_word(config); 641 pci_set_word(config, val & ~mask); 642 return val & mask; 643 } 644 645 static inline uint16_t 646 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 647 { 648 uint16_t val = pci_get_word(config); 649 pci_set_word(config, val | mask); 650 return val & mask; 651 } 652 653 static inline uint32_t 654 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 655 { 656 uint32_t val = pci_get_long(config); 657 pci_set_long(config, val & ~mask); 658 return val & mask; 659 } 660 661 static inline uint32_t 662 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 663 { 664 uint32_t val = pci_get_long(config); 665 pci_set_long(config, val | mask); 666 return val & mask; 667 } 668 669 static inline uint64_t 670 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 671 { 672 uint64_t val = pci_get_quad(config); 673 pci_set_quad(config, val & ~mask); 674 return val & mask; 675 } 676 677 static inline uint64_t 678 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 679 { 680 uint64_t val = pci_get_quad(config); 681 pci_set_quad(config, val | mask); 682 return val & mask; 683 } 684 685 /* Access a register specified by a mask */ 686 static inline void 687 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 688 { 689 uint8_t val = pci_get_byte(config); 690 uint8_t rval; 691 692 assert(mask); 693 rval = reg << ctz32(mask); 694 pci_set_byte(config, (~mask & val) | (mask & rval)); 695 } 696 697 static inline void 698 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 699 { 700 uint16_t val = pci_get_word(config); 701 uint16_t rval; 702 703 assert(mask); 704 rval = reg << ctz32(mask); 705 pci_set_word(config, (~mask & val) | (mask & rval)); 706 } 707 708 static inline void 709 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 710 { 711 uint32_t val = pci_get_long(config); 712 uint32_t rval; 713 714 assert(mask); 715 rval = reg << ctz32(mask); 716 pci_set_long(config, (~mask & val) | (mask & rval)); 717 } 718 719 static inline void 720 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 721 { 722 uint64_t val = pci_get_quad(config); 723 uint64_t rval; 724 725 assert(mask); 726 rval = reg << ctz32(mask); 727 pci_set_quad(config, (~mask & val) | (mask & rval)); 728 } 729 730 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 731 const char *name); 732 PCIDevice *pci_new(int devfn, const char *name); 733 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 734 735 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 736 bool multifunction, 737 const char *name); 738 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 739 740 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 741 742 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 743 void pci_set_irq(PCIDevice *pci_dev, int level); 744 745 static inline int pci_intx(PCIDevice *pci_dev) 746 { 747 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 748 } 749 750 static inline void pci_irq_assert(PCIDevice *pci_dev) 751 { 752 pci_set_irq(pci_dev, 1); 753 } 754 755 static inline void pci_irq_deassert(PCIDevice *pci_dev) 756 { 757 pci_set_irq(pci_dev, 0); 758 } 759 760 /* 761 * FIXME: PCI does not work this way. 762 * All the callers to this method should be fixed. 763 */ 764 static inline void pci_irq_pulse(PCIDevice *pci_dev) 765 { 766 pci_irq_assert(pci_dev); 767 pci_irq_deassert(pci_dev); 768 } 769 770 static inline int pci_is_cxl(const PCIDevice *d) 771 { 772 return d->cap_present & QEMU_PCIE_CAP_CXL; 773 } 774 775 static inline int pci_is_express(const PCIDevice *d) 776 { 777 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 778 } 779 780 static inline int pci_is_express_downstream_port(const PCIDevice *d) 781 { 782 uint8_t type; 783 784 if (!pci_is_express(d) || !d->exp.exp_cap) { 785 return 0; 786 } 787 788 type = pcie_cap_get_type(d); 789 790 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 791 } 792 793 static inline int pci_is_vf(const PCIDevice *d) 794 { 795 return d->exp.sriov_vf.pf != NULL; 796 } 797 798 static inline uint32_t pci_config_size(const PCIDevice *d) 799 { 800 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 801 } 802 803 static inline uint16_t pci_get_bdf(PCIDevice *dev) 804 { 805 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 806 } 807 808 uint16_t pci_requester_id(PCIDevice *dev); 809 810 /* DMA access functions */ 811 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 812 { 813 return &dev->bus_master_as; 814 } 815 816 /** 817 * pci_dma_rw: Read from or write to an address space from PCI device. 818 * 819 * Return a MemTxResult indicating whether the operation succeeded 820 * or failed (eg unassigned memory, device rejected the transaction, 821 * IOMMU fault). 822 * 823 * @dev: #PCIDevice doing the memory access 824 * @addr: address within the #PCIDevice address space 825 * @buf: buffer with the data transferred 826 * @len: the number of bytes to read or write 827 * @dir: indicates the transfer direction 828 */ 829 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 830 void *buf, dma_addr_t len, 831 DMADirection dir, MemTxAttrs attrs) 832 { 833 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 834 dir, attrs); 835 } 836 837 /** 838 * pci_dma_read: Read from an address space from PCI device. 839 * 840 * Return a MemTxResult indicating whether the operation succeeded 841 * or failed (eg unassigned memory, device rejected the transaction, 842 * IOMMU fault). Called within RCU critical section. 843 * 844 * @dev: #PCIDevice doing the memory access 845 * @addr: address within the #PCIDevice address space 846 * @buf: buffer with the data transferred 847 * @len: length of the data transferred 848 */ 849 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 850 void *buf, dma_addr_t len) 851 { 852 return pci_dma_rw(dev, addr, buf, len, 853 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 854 } 855 856 /** 857 * pci_dma_write: Write to address space from PCI device. 858 * 859 * Return a MemTxResult indicating whether the operation succeeded 860 * or failed (eg unassigned memory, device rejected the transaction, 861 * IOMMU fault). 862 * 863 * @dev: #PCIDevice doing the memory access 864 * @addr: address within the #PCIDevice address space 865 * @buf: buffer with the data transferred 866 * @len: the number of bytes to write 867 */ 868 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 869 const void *buf, dma_addr_t len) 870 { 871 return pci_dma_rw(dev, addr, (void *) buf, len, 872 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 873 } 874 875 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 876 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 877 dma_addr_t addr, \ 878 uint##_bits##_t *val, \ 879 MemTxAttrs attrs) \ 880 { \ 881 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 882 } \ 883 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 884 dma_addr_t addr, \ 885 uint##_bits##_t val, \ 886 MemTxAttrs attrs) \ 887 { \ 888 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 889 } 890 891 PCI_DMA_DEFINE_LDST(ub, b, 8); 892 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 893 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 894 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 895 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 896 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 897 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 898 899 #undef PCI_DMA_DEFINE_LDST 900 901 /** 902 * pci_dma_map: Map device PCI address space range into host virtual address 903 * @dev: #PCIDevice to be accessed 904 * @addr: address within that device's address space 905 * @plen: pointer to length of buffer; updated on return to indicate 906 * if only a subset of the requested range has been mapped 907 * @dir: indicates the transfer direction 908 * 909 * Return: A host pointer, or %NULL if the resources needed to 910 * perform the mapping are exhausted (in that case *@plen 911 * is set to zero). 912 */ 913 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 914 dma_addr_t *plen, DMADirection dir) 915 { 916 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 917 MEMTXATTRS_UNSPECIFIED); 918 } 919 920 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 921 DMADirection dir, dma_addr_t access_len) 922 { 923 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 924 } 925 926 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 927 int alloc_hint) 928 { 929 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 930 } 931 932 extern const VMStateDescription vmstate_pci_device; 933 934 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 935 .name = (stringify(_field)), \ 936 .size = sizeof(PCIDevice), \ 937 .vmsd = &vmstate_pci_device, \ 938 .flags = VMS_STRUCT, \ 939 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 940 } 941 942 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 943 .name = (stringify(_field)), \ 944 .size = sizeof(PCIDevice), \ 945 .vmsd = &vmstate_pci_device, \ 946 .flags = VMS_STRUCT|VMS_POINTER, \ 947 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 948 } 949 950 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 951 void pci_set_power(PCIDevice *pci_dev, bool state); 952 953 #endif 954