1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 10 /* PCI includes legacy ISA access. */ 11 #include "hw/isa/isa.h" 12 13 #include "hw/pci/pcie.h" 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 19 #define PCI_FUNC(devfn) ((devfn) & 0x07) 20 #define PCI_SLOT_MAX 32 21 #define PCI_FUNC_MAX 8 22 23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 24 #include "hw/pci/pci_ids.h" 25 26 /* QEMU-specific Vendor and Device ID definitions */ 27 28 /* IBM (0x1014) */ 29 #define PCI_DEVICE_ID_IBM_440GX 0x027f 30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 31 32 /* Hitachi (0x1054) */ 33 #define PCI_VENDOR_ID_HITACHI 0x1054 34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 35 36 /* Apple (0x106b) */ 37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 42 43 /* Realtek (0x10ec) */ 44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 45 46 /* Xilinx (0x10ee) */ 47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 48 49 /* Marvell (0x11ab) */ 50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 51 52 /* QEMU/Bochs VGA (0x1234) */ 53 #define PCI_VENDOR_ID_QEMU 0x1234 54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 55 56 /* VMWare (0x15ad) */ 57 #define PCI_VENDOR_ID_VMWARE 0x15ad 58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 62 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 63 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 64 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 65 66 /* Intel (0x8086) */ 67 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 68 #define PCI_DEVICE_ID_INTEL_82557 0x1229 69 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 70 71 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 72 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 73 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBDEVICE_ID_QEMU 0x1100 75 76 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 77 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 78 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 79 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 80 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 81 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 82 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 83 84 #define PCI_VENDOR_ID_REDHAT 0x1b36 85 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 86 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 87 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 88 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 89 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 90 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 91 92 #define FMT_PCIBUS PRIx64 93 94 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 95 uint32_t address, uint32_t data, int len); 96 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 97 uint32_t address, int len); 98 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 99 pcibus_t addr, pcibus_t size, int type); 100 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 101 102 typedef struct PCIIORegion { 103 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 104 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 105 pcibus_t size; 106 uint8_t type; 107 MemoryRegion *memory; 108 MemoryRegion *address_space; 109 } PCIIORegion; 110 111 #define PCI_ROM_SLOT 6 112 #define PCI_NUM_REGIONS 7 113 114 enum { 115 QEMU_PCI_VGA_MEM, 116 QEMU_PCI_VGA_IO_LO, 117 QEMU_PCI_VGA_IO_HI, 118 QEMU_PCI_VGA_NUM_REGIONS, 119 }; 120 121 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 122 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 123 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 124 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 125 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 126 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 127 128 #include "hw/pci/pci_regs.h" 129 130 /* PCI HEADER_TYPE */ 131 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 132 133 /* Size of the standard PCI config header */ 134 #define PCI_CONFIG_HEADER_SIZE 0x40 135 /* Size of the standard PCI config space */ 136 #define PCI_CONFIG_SPACE_SIZE 0x100 137 /* Size of the standart PCIe config space: 4KB */ 138 #define PCIE_CONFIG_SPACE_SIZE 0x1000 139 140 #define PCI_NUM_PINS 4 /* A-D */ 141 142 /* Bits in cap_present field. */ 143 enum { 144 QEMU_PCI_CAP_MSI = 0x1, 145 QEMU_PCI_CAP_MSIX = 0x2, 146 QEMU_PCI_CAP_EXPRESS = 0x4, 147 148 /* multifunction capable device */ 149 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 150 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 151 152 /* command register SERR bit enabled */ 153 #define QEMU_PCI_CAP_SERR_BITNR 4 154 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 155 /* Standard hot plug controller. */ 156 #define QEMU_PCI_SHPC_BITNR 5 157 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 158 #define QEMU_PCI_SLOTID_BITNR 6 159 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 160 }; 161 162 #define TYPE_PCI_DEVICE "pci-device" 163 #define PCI_DEVICE(obj) \ 164 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 165 #define PCI_DEVICE_CLASS(klass) \ 166 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 167 #define PCI_DEVICE_GET_CLASS(obj) \ 168 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 169 170 typedef struct PCIINTxRoute { 171 enum { 172 PCI_INTX_ENABLED, 173 PCI_INTX_INVERTED, 174 PCI_INTX_DISABLED, 175 } mode; 176 int irq; 177 } PCIINTxRoute; 178 179 typedef struct PCIDeviceClass { 180 DeviceClass parent_class; 181 182 int (*init)(PCIDevice *dev); 183 PCIUnregisterFunc *exit; 184 PCIConfigReadFunc *config_read; 185 PCIConfigWriteFunc *config_write; 186 187 uint16_t vendor_id; 188 uint16_t device_id; 189 uint8_t revision; 190 uint16_t class_id; 191 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 192 uint16_t subsystem_id; /* only for header type = 0 */ 193 194 /* 195 * pci-to-pci bridge or normal device. 196 * This doesn't mean pci host switch. 197 * When card bus bridge is supported, this would be enhanced. 198 */ 199 int is_bridge; 200 201 /* pcie stuff */ 202 int is_express; /* is this device pci express? */ 203 204 /* device isn't hot-pluggable */ 205 int no_hotplug; 206 207 /* rom bar */ 208 const char *romfile; 209 } PCIDeviceClass; 210 211 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 212 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 213 MSIMessage msg); 214 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 215 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 216 unsigned int vector_start, 217 unsigned int vector_end); 218 219 struct PCIDevice { 220 DeviceState qdev; 221 222 /* PCI config space */ 223 uint8_t *config; 224 225 /* Used to enable config checks on load. Note that writable bits are 226 * never checked even if set in cmask. */ 227 uint8_t *cmask; 228 229 /* Used to implement R/W bytes */ 230 uint8_t *wmask; 231 232 /* Used to implement RW1C(Write 1 to Clear) bytes */ 233 uint8_t *w1cmask; 234 235 /* Used to allocate config space for capabilities. */ 236 uint8_t *used; 237 238 /* the following fields are read only */ 239 PCIBus *bus; 240 int32_t devfn; 241 char name[64]; 242 PCIIORegion io_regions[PCI_NUM_REGIONS]; 243 AddressSpace bus_master_as; 244 MemoryRegion bus_master_enable_region; 245 DMAContext *dma; 246 247 /* do not access the following fields */ 248 PCIConfigReadFunc *config_read; 249 PCIConfigWriteFunc *config_write; 250 251 /* IRQ objects for the INTA-INTD pins. */ 252 qemu_irq *irq; 253 254 /* Legacy PCI VGA regions */ 255 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 256 bool has_vga; 257 258 /* Current IRQ levels. Used internally by the generic PCI code. */ 259 uint8_t irq_state; 260 261 /* Capability bits */ 262 uint32_t cap_present; 263 264 /* Offset of MSI-X capability in config space */ 265 uint8_t msix_cap; 266 267 /* MSI-X entries */ 268 int msix_entries_nr; 269 270 /* Space to store MSIX table & pending bit array */ 271 uint8_t *msix_table; 272 uint8_t *msix_pba; 273 /* MemoryRegion container for msix exclusive BAR setup */ 274 MemoryRegion msix_exclusive_bar; 275 /* Memory Regions for MSIX table and pending bit entries. */ 276 MemoryRegion msix_table_mmio; 277 MemoryRegion msix_pba_mmio; 278 /* Reference-count for entries actually in use by driver. */ 279 unsigned *msix_entry_used; 280 /* MSIX function mask set or MSIX disabled */ 281 bool msix_function_masked; 282 /* Version id needed for VMState */ 283 int32_t version_id; 284 285 /* Offset of MSI capability in config space */ 286 uint8_t msi_cap; 287 288 /* PCI Express */ 289 PCIExpressDevice exp; 290 291 /* SHPC */ 292 SHPCDevice *shpc; 293 294 /* Location of option rom */ 295 char *romfile; 296 bool has_rom; 297 MemoryRegion rom; 298 uint32_t rom_bar; 299 300 /* INTx routing notifier */ 301 PCIINTxRoutingNotifier intx_routing_notifier; 302 303 /* MSI-X notifiers */ 304 MSIVectorUseNotifier msix_vector_use_notifier; 305 MSIVectorReleaseNotifier msix_vector_release_notifier; 306 MSIVectorPollNotifier msix_vector_poll_notifier; 307 }; 308 309 void pci_register_bar(PCIDevice *pci_dev, int region_num, 310 uint8_t attr, MemoryRegion *memory); 311 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 312 MemoryRegion *io_lo, MemoryRegion *io_hi); 313 void pci_unregister_vga(PCIDevice *pci_dev); 314 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 315 316 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 317 uint8_t offset, uint8_t size); 318 319 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 320 321 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 322 323 324 uint32_t pci_default_read_config(PCIDevice *d, 325 uint32_t address, int len); 326 void pci_default_write_config(PCIDevice *d, 327 uint32_t address, uint32_t val, int len); 328 void pci_device_save(PCIDevice *s, QEMUFile *f); 329 int pci_device_load(PCIDevice *s, QEMUFile *f); 330 MemoryRegion *pci_address_space(PCIDevice *dev); 331 MemoryRegion *pci_address_space_io(PCIDevice *dev); 332 333 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 334 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 335 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 336 337 typedef enum { 338 PCI_HOTPLUG_DISABLED, 339 PCI_HOTPLUG_ENABLED, 340 PCI_COLDPLUG_ENABLED, 341 } PCIHotplugState; 342 343 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, 344 PCIHotplugState state); 345 346 #define TYPE_PCI_BUS "PCI" 347 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 348 #define TYPE_PCIE_BUS "PCIE" 349 350 bool pci_bus_is_express(PCIBus *bus); 351 bool pci_bus_is_root(PCIBus *bus); 352 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, 353 const char *name, 354 MemoryRegion *address_space_mem, 355 MemoryRegion *address_space_io, 356 uint8_t devfn_min, const char *typename); 357 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 358 MemoryRegion *address_space_mem, 359 MemoryRegion *address_space_io, 360 uint8_t devfn_min, const char *typename); 361 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 362 void *irq_opaque, int nirq); 363 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 364 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); 365 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 366 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 367 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 368 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 369 void *irq_opaque, 370 MemoryRegion *address_space_mem, 371 MemoryRegion *address_space_io, 372 uint8_t devfn_min, int nirq, const char *typename); 373 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 374 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 375 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 376 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 377 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 378 PCIINTxRoutingNotifier notifier); 379 void pci_device_reset(PCIDevice *dev); 380 void pci_bus_reset(PCIBus *bus); 381 382 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, 383 const char *default_devaddr); 384 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, 385 const char *default_devaddr); 386 387 PCIDevice *pci_vga_init(PCIBus *bus); 388 389 int pci_bus_num(PCIBus *s); 390 void pci_for_each_device(PCIBus *bus, int bus_num, 391 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 392 void *opaque); 393 PCIBus *pci_find_root_bus(int domain); 394 int pci_find_domain(const PCIBus *bus); 395 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 396 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 397 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); 398 399 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, 400 unsigned *slotp); 401 402 void pci_device_deassert_intx(PCIDevice *dev); 403 404 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); 405 406 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); 407 408 static inline void 409 pci_set_byte(uint8_t *config, uint8_t val) 410 { 411 *config = val; 412 } 413 414 static inline uint8_t 415 pci_get_byte(const uint8_t *config) 416 { 417 return *config; 418 } 419 420 static inline void 421 pci_set_word(uint8_t *config, uint16_t val) 422 { 423 cpu_to_le16wu((uint16_t *)config, val); 424 } 425 426 static inline uint16_t 427 pci_get_word(const uint8_t *config) 428 { 429 return le16_to_cpupu((const uint16_t *)config); 430 } 431 432 static inline void 433 pci_set_long(uint8_t *config, uint32_t val) 434 { 435 cpu_to_le32wu((uint32_t *)config, val); 436 } 437 438 static inline uint32_t 439 pci_get_long(const uint8_t *config) 440 { 441 return le32_to_cpupu((const uint32_t *)config); 442 } 443 444 static inline void 445 pci_set_quad(uint8_t *config, uint64_t val) 446 { 447 cpu_to_le64w((uint64_t *)config, val); 448 } 449 450 static inline uint64_t 451 pci_get_quad(const uint8_t *config) 452 { 453 return le64_to_cpup((const uint64_t *)config); 454 } 455 456 static inline void 457 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 458 { 459 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 460 } 461 462 static inline void 463 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 464 { 465 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 466 } 467 468 static inline void 469 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 470 { 471 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 472 } 473 474 static inline void 475 pci_config_set_class(uint8_t *pci_config, uint16_t val) 476 { 477 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 478 } 479 480 static inline void 481 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 482 { 483 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 484 } 485 486 static inline void 487 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 488 { 489 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 490 } 491 492 /* 493 * helper functions to do bit mask operation on configuration space. 494 * Just to set bit, use test-and-set and discard returned value. 495 * Just to clear bit, use test-and-clear and discard returned value. 496 * NOTE: They aren't atomic. 497 */ 498 static inline uint8_t 499 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 500 { 501 uint8_t val = pci_get_byte(config); 502 pci_set_byte(config, val & ~mask); 503 return val & mask; 504 } 505 506 static inline uint8_t 507 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 508 { 509 uint8_t val = pci_get_byte(config); 510 pci_set_byte(config, val | mask); 511 return val & mask; 512 } 513 514 static inline uint16_t 515 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 516 { 517 uint16_t val = pci_get_word(config); 518 pci_set_word(config, val & ~mask); 519 return val & mask; 520 } 521 522 static inline uint16_t 523 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 524 { 525 uint16_t val = pci_get_word(config); 526 pci_set_word(config, val | mask); 527 return val & mask; 528 } 529 530 static inline uint32_t 531 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 532 { 533 uint32_t val = pci_get_long(config); 534 pci_set_long(config, val & ~mask); 535 return val & mask; 536 } 537 538 static inline uint32_t 539 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 540 { 541 uint32_t val = pci_get_long(config); 542 pci_set_long(config, val | mask); 543 return val & mask; 544 } 545 546 static inline uint64_t 547 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 548 { 549 uint64_t val = pci_get_quad(config); 550 pci_set_quad(config, val & ~mask); 551 return val & mask; 552 } 553 554 static inline uint64_t 555 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 556 { 557 uint64_t val = pci_get_quad(config); 558 pci_set_quad(config, val | mask); 559 return val & mask; 560 } 561 562 /* Access a register specified by a mask */ 563 static inline void 564 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 565 { 566 uint8_t val = pci_get_byte(config); 567 uint8_t rval = reg << (ffs(mask) - 1); 568 pci_set_byte(config, (~mask & val) | (mask & rval)); 569 } 570 571 static inline uint8_t 572 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 573 { 574 uint8_t val = pci_get_byte(config); 575 return (val & mask) >> (ffs(mask) - 1); 576 } 577 578 static inline void 579 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 580 { 581 uint16_t val = pci_get_word(config); 582 uint16_t rval = reg << (ffs(mask) - 1); 583 pci_set_word(config, (~mask & val) | (mask & rval)); 584 } 585 586 static inline uint16_t 587 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 588 { 589 uint16_t val = pci_get_word(config); 590 return (val & mask) >> (ffs(mask) - 1); 591 } 592 593 static inline void 594 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 595 { 596 uint32_t val = pci_get_long(config); 597 uint32_t rval = reg << (ffs(mask) - 1); 598 pci_set_long(config, (~mask & val) | (mask & rval)); 599 } 600 601 static inline uint32_t 602 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 603 { 604 uint32_t val = pci_get_long(config); 605 return (val & mask) >> (ffs(mask) - 1); 606 } 607 608 static inline void 609 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 610 { 611 uint64_t val = pci_get_quad(config); 612 uint64_t rval = reg << (ffs(mask) - 1); 613 pci_set_quad(config, (~mask & val) | (mask & rval)); 614 } 615 616 static inline uint64_t 617 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 618 { 619 uint64_t val = pci_get_quad(config); 620 return (val & mask) >> (ffs(mask) - 1); 621 } 622 623 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 624 const char *name); 625 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 626 bool multifunction, 627 const char *name); 628 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 629 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 630 631 static inline int pci_is_express(const PCIDevice *d) 632 { 633 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 634 } 635 636 static inline uint32_t pci_config_size(const PCIDevice *d) 637 { 638 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 639 } 640 641 /* DMA access functions */ 642 static inline DMAContext *pci_dma_context(PCIDevice *dev) 643 { 644 return dev->dma; 645 } 646 647 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 648 void *buf, dma_addr_t len, DMADirection dir) 649 { 650 dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); 651 return 0; 652 } 653 654 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 655 void *buf, dma_addr_t len) 656 { 657 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 658 } 659 660 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 661 const void *buf, dma_addr_t len) 662 { 663 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 664 } 665 666 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 667 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 668 dma_addr_t addr) \ 669 { \ 670 return ld##_l##_dma(pci_dma_context(dev), addr); \ 671 } \ 672 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 673 dma_addr_t addr, uint##_bits##_t val) \ 674 { \ 675 st##_s##_dma(pci_dma_context(dev), addr, val); \ 676 } 677 678 PCI_DMA_DEFINE_LDST(ub, b, 8); 679 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 680 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 681 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 682 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 683 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 684 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 685 686 #undef PCI_DMA_DEFINE_LDST 687 688 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 689 dma_addr_t *plen, DMADirection dir) 690 { 691 void *buf; 692 693 buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); 694 return buf; 695 } 696 697 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 698 DMADirection dir, dma_addr_t access_len) 699 { 700 dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); 701 } 702 703 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 704 int alloc_hint) 705 { 706 qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); 707 } 708 709 extern const VMStateDescription vmstate_pci_device; 710 711 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 712 .name = (stringify(_field)), \ 713 .size = sizeof(PCIDevice), \ 714 .vmsd = &vmstate_pci_device, \ 715 .flags = VMS_STRUCT, \ 716 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 717 } 718 719 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 720 .name = (stringify(_field)), \ 721 .size = sizeof(PCIDevice), \ 722 .vmsd = &vmstate_pci_device, \ 723 .flags = VMS_STRUCT|VMS_POINTER, \ 724 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 725 } 726 727 #endif 728