1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 extern bool pci_available; 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 22 #define PCI_BUS_MAX 256 23 #define PCI_DEVFN_MAX 256 24 #define PCI_SLOT_MAX 32 25 #define PCI_FUNC_MAX 8 26 27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 28 #include "hw/pci/pci_ids.h" 29 30 /* QEMU-specific Vendor and Device ID definitions */ 31 32 /* IBM (0x1014) */ 33 #define PCI_DEVICE_ID_IBM_440GX 0x027f 34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 35 36 /* Hitachi (0x1054) */ 37 #define PCI_VENDOR_ID_HITACHI 0x1054 38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 39 40 /* Apple (0x106b) */ 41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 46 47 /* Realtek (0x10ec) */ 48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 49 50 /* Xilinx (0x10ee) */ 51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 52 53 /* Marvell (0x11ab) */ 54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 55 56 /* QEMU/Bochs VGA (0x1234) */ 57 #define PCI_VENDOR_ID_QEMU 0x1234 58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 59 60 /* VMWare (0x15ad) */ 61 #define PCI_VENDOR_ID_VMWARE 0x15ad 62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 69 70 /* Intel (0x8086) */ 71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 72 #define PCI_DEVICE_ID_INTEL_82557 0x1229 73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 74 75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBDEVICE_ID_QEMU 0x1100 79 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 #define PCI_VENDOR_ID_REDHAT 0x1b36 90 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 91 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 92 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 93 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 94 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 95 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 96 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 97 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 98 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 100 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 101 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 102 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 103 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 104 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 105 106 #define FMT_PCIBUS PRIx64 107 108 typedef uint64_t pcibus_t; 109 110 struct PCIHostDeviceAddress { 111 unsigned int domain; 112 unsigned int bus; 113 unsigned int slot; 114 unsigned int function; 115 }; 116 117 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 118 uint32_t address, uint32_t data, int len); 119 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 120 uint32_t address, int len); 121 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 122 pcibus_t addr, pcibus_t size, int type); 123 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 124 125 typedef struct PCIIORegion { 126 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 127 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 128 pcibus_t size; 129 uint8_t type; 130 MemoryRegion *memory; 131 MemoryRegion *address_space; 132 } PCIIORegion; 133 134 #define PCI_ROM_SLOT 6 135 #define PCI_NUM_REGIONS 7 136 137 enum { 138 QEMU_PCI_VGA_MEM, 139 QEMU_PCI_VGA_IO_LO, 140 QEMU_PCI_VGA_IO_HI, 141 QEMU_PCI_VGA_NUM_REGIONS, 142 }; 143 144 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 145 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 146 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 147 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 148 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 149 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 150 151 #include "hw/pci/pci_regs.h" 152 153 /* PCI HEADER_TYPE */ 154 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 155 156 /* Size of the standard PCI config header */ 157 #define PCI_CONFIG_HEADER_SIZE 0x40 158 /* Size of the standard PCI config space */ 159 #define PCI_CONFIG_SPACE_SIZE 0x100 160 /* Size of the standard PCIe config space: 4KB */ 161 #define PCIE_CONFIG_SPACE_SIZE 0x1000 162 163 #define PCI_NUM_PINS 4 /* A-D */ 164 165 /* Bits in cap_present field. */ 166 enum { 167 QEMU_PCI_CAP_MSI = 0x1, 168 QEMU_PCI_CAP_MSIX = 0x2, 169 QEMU_PCI_CAP_EXPRESS = 0x4, 170 171 /* multifunction capable device */ 172 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 173 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 174 175 /* command register SERR bit enabled */ 176 #define QEMU_PCI_CAP_SERR_BITNR 4 177 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 178 /* Standard hot plug controller. */ 179 #define QEMU_PCI_SHPC_BITNR 5 180 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 181 #define QEMU_PCI_SLOTID_BITNR 6 182 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 183 /* PCI Express capability - Power Controller Present */ 184 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 185 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 186 /* Link active status in endpoint capability is always set */ 187 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 188 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 189 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 190 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 191 }; 192 193 #define TYPE_PCI_DEVICE "pci-device" 194 #define PCI_DEVICE(obj) \ 195 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 196 #define PCI_DEVICE_CLASS(klass) \ 197 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 198 #define PCI_DEVICE_GET_CLASS(obj) \ 199 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 200 201 typedef struct PCIINTxRoute { 202 enum { 203 PCI_INTX_ENABLED, 204 PCI_INTX_INVERTED, 205 PCI_INTX_DISABLED, 206 } mode; 207 int irq; 208 } PCIINTxRoute; 209 210 typedef struct PCIDeviceClass { 211 DeviceClass parent_class; 212 213 void (*realize)(PCIDevice *dev, Error **errp); 214 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 215 PCIUnregisterFunc *exit; 216 PCIConfigReadFunc *config_read; 217 PCIConfigWriteFunc *config_write; 218 219 uint16_t vendor_id; 220 uint16_t device_id; 221 uint8_t revision; 222 uint16_t class_id; 223 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 224 uint16_t subsystem_id; /* only for header type = 0 */ 225 226 /* 227 * pci-to-pci bridge or normal device. 228 * This doesn't mean pci host switch. 229 * When card bus bridge is supported, this would be enhanced. 230 */ 231 int is_bridge; 232 233 /* pcie stuff */ 234 int is_express; /* is this device pci express? */ 235 236 /* rom bar */ 237 const char *romfile; 238 } PCIDeviceClass; 239 240 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 241 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 242 MSIMessage msg); 243 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 244 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 245 unsigned int vector_start, 246 unsigned int vector_end); 247 248 enum PCIReqIDType { 249 PCI_REQ_ID_INVALID = 0, 250 PCI_REQ_ID_BDF, 251 PCI_REQ_ID_SECONDARY_BUS, 252 PCI_REQ_ID_MAX, 253 }; 254 typedef enum PCIReqIDType PCIReqIDType; 255 256 struct PCIReqIDCache { 257 PCIDevice *dev; 258 PCIReqIDType type; 259 }; 260 typedef struct PCIReqIDCache PCIReqIDCache; 261 262 struct PCIDevice { 263 DeviceState qdev; 264 265 /* PCI config space */ 266 uint8_t *config; 267 268 /* Used to enable config checks on load. Note that writable bits are 269 * never checked even if set in cmask. */ 270 uint8_t *cmask; 271 272 /* Used to implement R/W bytes */ 273 uint8_t *wmask; 274 275 /* Used to implement RW1C(Write 1 to Clear) bytes */ 276 uint8_t *w1cmask; 277 278 /* Used to allocate config space for capabilities. */ 279 uint8_t *used; 280 281 /* the following fields are read only */ 282 PCIBus *bus; 283 int32_t devfn; 284 /* Cached device to fetch requester ID from, to avoid the PCI 285 * tree walking every time we invoke PCI request (e.g., 286 * MSI). For conventional PCI root complex, this field is 287 * meaningless. */ 288 PCIReqIDCache requester_id_cache; 289 char name[64]; 290 PCIIORegion io_regions[PCI_NUM_REGIONS]; 291 AddressSpace bus_master_as; 292 MemoryRegion bus_master_container_region; 293 MemoryRegion bus_master_enable_region; 294 295 /* do not access the following fields */ 296 PCIConfigReadFunc *config_read; 297 PCIConfigWriteFunc *config_write; 298 299 /* Legacy PCI VGA regions */ 300 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 301 bool has_vga; 302 303 /* Current IRQ levels. Used internally by the generic PCI code. */ 304 uint8_t irq_state; 305 306 /* Capability bits */ 307 uint32_t cap_present; 308 309 /* Offset of MSI-X capability in config space */ 310 uint8_t msix_cap; 311 312 /* MSI-X entries */ 313 int msix_entries_nr; 314 315 /* Space to store MSIX table & pending bit array */ 316 uint8_t *msix_table; 317 uint8_t *msix_pba; 318 /* MemoryRegion container for msix exclusive BAR setup */ 319 MemoryRegion msix_exclusive_bar; 320 /* Memory Regions for MSIX table and pending bit entries. */ 321 MemoryRegion msix_table_mmio; 322 MemoryRegion msix_pba_mmio; 323 /* Reference-count for entries actually in use by driver. */ 324 unsigned *msix_entry_used; 325 /* MSIX function mask set or MSIX disabled */ 326 bool msix_function_masked; 327 /* Version id needed for VMState */ 328 int32_t version_id; 329 330 /* Offset of MSI capability in config space */ 331 uint8_t msi_cap; 332 333 /* PCI Express */ 334 PCIExpressDevice exp; 335 336 /* SHPC */ 337 SHPCDevice *shpc; 338 339 /* Location of option rom */ 340 char *romfile; 341 bool has_rom; 342 MemoryRegion rom; 343 uint32_t rom_bar; 344 345 /* INTx routing notifier */ 346 PCIINTxRoutingNotifier intx_routing_notifier; 347 348 /* MSI-X notifiers */ 349 MSIVectorUseNotifier msix_vector_use_notifier; 350 MSIVectorReleaseNotifier msix_vector_release_notifier; 351 MSIVectorPollNotifier msix_vector_poll_notifier; 352 }; 353 354 void pci_register_bar(PCIDevice *pci_dev, int region_num, 355 uint8_t attr, MemoryRegion *memory); 356 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 357 MemoryRegion *io_lo, MemoryRegion *io_hi); 358 void pci_unregister_vga(PCIDevice *pci_dev); 359 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 360 361 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 362 uint8_t offset, uint8_t size, 363 Error **errp); 364 365 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 366 367 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 368 369 370 uint32_t pci_default_read_config(PCIDevice *d, 371 uint32_t address, int len); 372 void pci_default_write_config(PCIDevice *d, 373 uint32_t address, uint32_t val, int len); 374 void pci_device_save(PCIDevice *s, QEMUFile *f); 375 int pci_device_load(PCIDevice *s, QEMUFile *f); 376 MemoryRegion *pci_address_space(PCIDevice *dev); 377 MemoryRegion *pci_address_space_io(PCIDevice *dev); 378 379 /* 380 * Should not normally be used by devices. For use by sPAPR target 381 * where QEMU emulates firmware. 382 */ 383 int pci_bar(PCIDevice *d, int reg); 384 385 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 386 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 387 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 388 389 #define TYPE_PCI_BUS "PCI" 390 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 391 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 392 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 393 #define TYPE_PCIE_BUS "PCIE" 394 395 bool pci_bus_is_express(PCIBus *bus); 396 bool pci_bus_is_root(PCIBus *bus); 397 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 398 const char *name, 399 MemoryRegion *address_space_mem, 400 MemoryRegion *address_space_io, 401 uint8_t devfn_min, const char *typename); 402 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 403 MemoryRegion *address_space_mem, 404 MemoryRegion *address_space_io, 405 uint8_t devfn_min, const char *typename); 406 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 407 void *irq_opaque, int nirq); 408 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 409 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 410 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 411 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 412 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 413 void *irq_opaque, 414 MemoryRegion *address_space_mem, 415 MemoryRegion *address_space_io, 416 uint8_t devfn_min, int nirq, const char *typename); 417 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 418 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 419 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 420 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 421 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 422 PCIINTxRoutingNotifier notifier); 423 void pci_device_reset(PCIDevice *dev); 424 425 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 426 const char *default_model, 427 const char *default_devaddr); 428 429 PCIDevice *pci_vga_init(PCIBus *bus); 430 431 int pci_bus_num(PCIBus *s); 432 int pci_bus_numa_node(PCIBus *bus); 433 void pci_for_each_device(PCIBus *bus, int bus_num, 434 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 435 void *opaque); 436 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 437 void (*fn)(PCIBus *bus, PCIDevice *d, 438 void *opaque), 439 void *opaque); 440 void pci_for_each_bus_depth_first(PCIBus *bus, 441 void *(*begin)(PCIBus *bus, void *parent_state), 442 void (*end)(PCIBus *bus, void *state), 443 void *parent_state); 444 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 445 446 /* Use this wrapper when specific scan order is not required. */ 447 static inline 448 void pci_for_each_bus(PCIBus *bus, 449 void (*fn)(PCIBus *bus, void *opaque), 450 void *opaque) 451 { 452 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 453 } 454 455 PCIBus *pci_find_primary_bus(void); 456 PCIBus *pci_device_root_bus(const PCIDevice *d); 457 const char *pci_root_bus_path(PCIDevice *dev); 458 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 459 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 460 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 461 462 void pci_device_deassert_intx(PCIDevice *dev); 463 464 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 465 466 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 467 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 468 469 static inline void 470 pci_set_byte(uint8_t *config, uint8_t val) 471 { 472 *config = val; 473 } 474 475 static inline uint8_t 476 pci_get_byte(const uint8_t *config) 477 { 478 return *config; 479 } 480 481 static inline void 482 pci_set_word(uint8_t *config, uint16_t val) 483 { 484 stw_le_p(config, val); 485 } 486 487 static inline uint16_t 488 pci_get_word(const uint8_t *config) 489 { 490 return lduw_le_p(config); 491 } 492 493 static inline void 494 pci_set_long(uint8_t *config, uint32_t val) 495 { 496 stl_le_p(config, val); 497 } 498 499 static inline uint32_t 500 pci_get_long(const uint8_t *config) 501 { 502 return ldl_le_p(config); 503 } 504 505 /* 506 * PCI capabilities and/or their fields 507 * are generally DWORD aligned only so 508 * mechanism used by pci_set/get_quad() 509 * must be tolerant to unaligned pointers 510 * 511 */ 512 static inline void 513 pci_set_quad(uint8_t *config, uint64_t val) 514 { 515 stq_le_p(config, val); 516 } 517 518 static inline uint64_t 519 pci_get_quad(const uint8_t *config) 520 { 521 return ldq_le_p(config); 522 } 523 524 static inline void 525 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 526 { 527 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 528 } 529 530 static inline void 531 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 532 { 533 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 534 } 535 536 static inline void 537 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 538 { 539 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 540 } 541 542 static inline void 543 pci_config_set_class(uint8_t *pci_config, uint16_t val) 544 { 545 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 546 } 547 548 static inline void 549 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 550 { 551 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 552 } 553 554 static inline void 555 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 556 { 557 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 558 } 559 560 /* 561 * helper functions to do bit mask operation on configuration space. 562 * Just to set bit, use test-and-set and discard returned value. 563 * Just to clear bit, use test-and-clear and discard returned value. 564 * NOTE: They aren't atomic. 565 */ 566 static inline uint8_t 567 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 568 { 569 uint8_t val = pci_get_byte(config); 570 pci_set_byte(config, val & ~mask); 571 return val & mask; 572 } 573 574 static inline uint8_t 575 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 576 { 577 uint8_t val = pci_get_byte(config); 578 pci_set_byte(config, val | mask); 579 return val & mask; 580 } 581 582 static inline uint16_t 583 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 584 { 585 uint16_t val = pci_get_word(config); 586 pci_set_word(config, val & ~mask); 587 return val & mask; 588 } 589 590 static inline uint16_t 591 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 592 { 593 uint16_t val = pci_get_word(config); 594 pci_set_word(config, val | mask); 595 return val & mask; 596 } 597 598 static inline uint32_t 599 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 600 { 601 uint32_t val = pci_get_long(config); 602 pci_set_long(config, val & ~mask); 603 return val & mask; 604 } 605 606 static inline uint32_t 607 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 608 { 609 uint32_t val = pci_get_long(config); 610 pci_set_long(config, val | mask); 611 return val & mask; 612 } 613 614 static inline uint64_t 615 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 616 { 617 uint64_t val = pci_get_quad(config); 618 pci_set_quad(config, val & ~mask); 619 return val & mask; 620 } 621 622 static inline uint64_t 623 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 624 { 625 uint64_t val = pci_get_quad(config); 626 pci_set_quad(config, val | mask); 627 return val & mask; 628 } 629 630 /* Access a register specified by a mask */ 631 static inline void 632 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 633 { 634 uint8_t val = pci_get_byte(config); 635 uint8_t rval = reg << ctz32(mask); 636 pci_set_byte(config, (~mask & val) | (mask & rval)); 637 } 638 639 static inline uint8_t 640 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 641 { 642 uint8_t val = pci_get_byte(config); 643 return (val & mask) >> ctz32(mask); 644 } 645 646 static inline void 647 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 648 { 649 uint16_t val = pci_get_word(config); 650 uint16_t rval = reg << ctz32(mask); 651 pci_set_word(config, (~mask & val) | (mask & rval)); 652 } 653 654 static inline uint16_t 655 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 656 { 657 uint16_t val = pci_get_word(config); 658 return (val & mask) >> ctz32(mask); 659 } 660 661 static inline void 662 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 663 { 664 uint32_t val = pci_get_long(config); 665 uint32_t rval = reg << ctz32(mask); 666 pci_set_long(config, (~mask & val) | (mask & rval)); 667 } 668 669 static inline uint32_t 670 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 671 { 672 uint32_t val = pci_get_long(config); 673 return (val & mask) >> ctz32(mask); 674 } 675 676 static inline void 677 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 678 { 679 uint64_t val = pci_get_quad(config); 680 uint64_t rval = reg << ctz32(mask); 681 pci_set_quad(config, (~mask & val) | (mask & rval)); 682 } 683 684 static inline uint64_t 685 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 686 { 687 uint64_t val = pci_get_quad(config); 688 return (val & mask) >> ctz32(mask); 689 } 690 691 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 692 const char *name); 693 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 694 bool multifunction, 695 const char *name); 696 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 697 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 698 699 void lsi53c895a_create(PCIBus *bus); 700 701 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 702 void pci_set_irq(PCIDevice *pci_dev, int level); 703 704 static inline void pci_irq_assert(PCIDevice *pci_dev) 705 { 706 pci_set_irq(pci_dev, 1); 707 } 708 709 static inline void pci_irq_deassert(PCIDevice *pci_dev) 710 { 711 pci_set_irq(pci_dev, 0); 712 } 713 714 /* 715 * FIXME: PCI does not work this way. 716 * All the callers to this method should be fixed. 717 */ 718 static inline void pci_irq_pulse(PCIDevice *pci_dev) 719 { 720 pci_irq_assert(pci_dev); 721 pci_irq_deassert(pci_dev); 722 } 723 724 static inline int pci_is_express(const PCIDevice *d) 725 { 726 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 727 } 728 729 static inline uint32_t pci_config_size(const PCIDevice *d) 730 { 731 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 732 } 733 734 static inline uint16_t pci_get_bdf(PCIDevice *dev) 735 { 736 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 737 } 738 739 uint16_t pci_requester_id(PCIDevice *dev); 740 741 /* DMA access functions */ 742 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 743 { 744 return &dev->bus_master_as; 745 } 746 747 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 748 void *buf, dma_addr_t len, DMADirection dir) 749 { 750 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 751 return 0; 752 } 753 754 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 755 void *buf, dma_addr_t len) 756 { 757 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 758 } 759 760 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 761 const void *buf, dma_addr_t len) 762 { 763 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 764 } 765 766 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 767 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 768 dma_addr_t addr) \ 769 { \ 770 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 771 } \ 772 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 773 dma_addr_t addr, uint##_bits##_t val) \ 774 { \ 775 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 776 } 777 778 PCI_DMA_DEFINE_LDST(ub, b, 8); 779 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 780 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 781 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 782 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 783 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 784 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 785 786 #undef PCI_DMA_DEFINE_LDST 787 788 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 789 dma_addr_t *plen, DMADirection dir) 790 { 791 void *buf; 792 793 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 794 return buf; 795 } 796 797 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 798 DMADirection dir, dma_addr_t access_len) 799 { 800 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 801 } 802 803 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 804 int alloc_hint) 805 { 806 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 807 } 808 809 extern const VMStateDescription vmstate_pci_device; 810 811 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 812 .name = (stringify(_field)), \ 813 .size = sizeof(PCIDevice), \ 814 .vmsd = &vmstate_pci_device, \ 815 .flags = VMS_STRUCT, \ 816 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 817 } 818 819 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 820 .name = (stringify(_field)), \ 821 .size = sizeof(PCIDevice), \ 822 .vmsd = &vmstate_pci_device, \ 823 .flags = VMS_STRUCT|VMS_POINTER, \ 824 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 825 } 826 827 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 828 829 #endif 830